PM7382-PI datasheet(48/330 Pages) PMC

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PM7382 FREEDM-32P256

DATA SHEET

PMC-2010333

ISSUE 3

FRAME ENGINE AND DATA LINK MANAGER 32P256

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

one flag byte must exist between HDLC packets for delineation. Contiguous flag

bytes, or all ones bytes between packets are used as an "inter-frame time fill".

Adjacent flag bytes may share zeros.

Figure 2 – HDLC Frame

Flag

Information

FCS

Flag

HDLC Packet

Flag

The CRC algorithm for the frame checking sequence (FCS) field is either a

CRC-CCITT or CRC-32 function. Figure 3 shows a CRC encoder block diagram

using the generating polynomial g(X) = 1 + g1X + g2X2 +…+ gn-1Xn-1 + Xn. The

CRC-CCITT FCS is two bytes in size and has a generating polynomial g(X) = 1 +

X5 + X12 + X16. The CRC-32 FCS is four bytes in size and has a generating

polynomial g(X) = 1 + X + X2 + X4 + X5 + X7 + X8 + X10 + X11 + X12 + X16 + X22

+ X23 + X26 + X32. The first FCS bit received is the residue of the highest term.

Figure 3 – CRC Generator

Dn-1

Message

Parity Check Digits

gn-1

LSB

MSB

8.3 Receive Channel Assigner

The Receive Channel Assigner block (RCAS256) processes up to 32 serial links.

Links may be configured to support 2.048 or 8.192 Mbps H-MVIP traffic, to

support T1/J1/E1 channelised traffic or to support unchannelised traffic. When

configured to support 2.048 Mbps H-MVIP traffic, each group of 8 links share a

clock and frame pulse. All links configured for 8.192 Mbps H-MVIP traffic share

a common clock and frame pulse. For T1/J1/E1 channelised traffic or for

unchannelised traffic, each link is independent and has its own associated clock.

For each link, the RCAS256 performs a serial to parallel conversion to form data

bytes. The data bytes are multiplexed, in byte serial format, for delivery to the

Receive HDLC Processor / Partial Packet Buffer block (RHDL256) at SYSCLK

rate. In the event where multiple streams have accumulated a byte of data,

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