PM7382-PI datasheet(49/330 Pages) PMC

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PM7382 FREEDM-32P256

DATA SHEET

PMC-2010333

ISSUE 3

FRAME ENGINE AND DATA LINK MANAGER 32P256

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

multiplexing is performed on a fixed priority basis with link #0 having the highest

priority and link #31 the lowest.

From the point of view of the RCAS256, links configured for H-MVIP traffic

behave identically to links configured for T1/J1/E1 channelised or unchannelised

traffic in the back end, only differing on the link side as described herein. First,

the number of time-slots in each frame is programmable to be 32 or 128 and has

an associated data clock frequency that is double the data rate. This provides

more bandwidth per link for applications requiring higher data densities on a

single link. Second, H-MVIP links reference the start of each frame with a frame

pulse, thereby avoiding having to gap the link clock during the framing bits/bytes

of each frame. The frame pulse is provided by an H-MVIP bus master and

ensures that all agents sharing the H-MVIP bus remain synchronized. When

configured for operation in 2.048 Mbps mode, the frame pulse is sampled using

the same clock which samples the data. When configured for operation in 8.192

Mbps H-MVIP mode, the frame pulse is sampled using a separate frame pulse

clock provided by an H-MVIP bus master. The frame pulse clock has a

synchronous timing relationship to the data clock. Third, not all links are

independent. When configured for operation in 2.048 Mbps H-MVIP mode, each

group of 8 links share a clock and a frame pulse. Links 0 through 7, 8 through

15, 16 through 23 and 24 through 31 each share a clock and a frame pulse. Not

all 8 links within each group need to be configured for operation in 2.048 Mbps

H-MVIP mode. However, any link within each logical group of 8 which is

configured for 2.048 Mbps H-MVIP operation will share the same clock and

frame pulse. When configured for operation in 8.192 Mbps H-MVIP mode, links

4m (0

£m£7) share a frame pulse, a data clock and a frame pulse clock. Again,

not all eight 4m (0

£m£7) links need to be configured for operation in 8.192 Mbps

H-MVIP mode, however, any link which is configured for 8.192 Mbps H-MVIP

operation will share the same frame pulse, data clock and frame pulse clock. If

link 4m is configured for 8.192 Mbps H-MVIP operation, then data transferred on

that link is “spread” over links 4m, 4m+1, 4m+2 and 4m+3 from a channel

assigner point of view. Accordingly, when link 4m is configured for operation in

8.192 Mbps H-MVIP mode, links 4m+1, 4m+2 and 4m+3 must also be

configured for operation in 8.192 Mbps H-MVIP mode. In the back end, the

RCAS256 extracts and processes the time-slots in the same way as channelised

T1/J1/E1 traffic.

Links containing a T1/J1 or an E1 stream may be channelised. Data at each

time-slot may be independently assigned to a different channel. The RCAS256

performs a table lookup to associate the link and time-slot identity with a

channel. T1/J1 and E1 framing bits/bytes are identified by observing the gap in

the link clock which is squelched during the framing bits/bytes. For

unchannelised links, clock rates are limited to 51.84 MHz for links #0 to #2 and

limited to 10 MHz for the remaining links. All data on each link belongs to one

channel. For the case of a mixture of channelised, unchannelised and H-MVIP

PM7382-PI Datasheet(PDF) 49 Page - PMC-Sierra, Inc

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