MIC2800 datasheet(18/32 Pages) MICROCHIP

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MIC2800

DS20005839C-page 18

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3.5

The switch (SW) pin is the common connection

between the internal power MOSFETs and connects

directly to the inductor. Due to the high-speed switching

on this pin, the switch node should be routed away from

sensitive nodes.

3.6

VIN

Two input voltage pins provide power to the switch

mode DC/DC and LDO2 separately. The LDO1 input

voltage is provided by the DC/DC LDO pin. VIN

provides power to the LDO section and the bias

through an internal 6Ω resistor. Both VIN pins must be

tied together.

For the switch mode DC/DC regulator, VIN provides

power to the MOSFET along with current limiting

sensing. Due to the high switching speeds, a 4.7 µF

minimum ceramic capacitor is recommended close to

VIN and the power ground (PGND) pin for bypassing.

3.7

LDO2

Regulated output voltage of LDO2. Power is provided

VIN.

The

minimum

recommended

output

capacitance is 2.2 µF ceramic.

3.8

Connect the feedback pin to VOUT for fixed output

voltage versions. For adjustable output version, an

external resistor divider is used to program the output

voltage. To calculate the resistor divider values for the

MIC2800, Equation 3-1 can be used. RTOP is

connected to VOUT, RBOT is connected to GND and

both are connected to the FB input pin.

EQUATION 3-1:

3.9

LDO

The LDO pin is the output of the LOWQ mode linear

regulator and should be connected to the output of the

DC/DC converter. In LOWQ mode (LOWQ < 0.2V), the

LDO supplies the output current and supports the

output voltage in place of the DC/DC stage. In PWM

mode (LOWQ > 1V) the LDO pin provides power to

LDO1.

3.10

LDO1

Regulated output voltage of LDO1. Input power is

provided by the DC/DC switching regulator. The

minimum recommended output capacitance is 2.2 µF

ceramic.

3.11

Power-on Reset (POR)

The Power-on Reset (POR) output is an open-drain

N-channel device, requiring a pull-up resistor to either

the input voltage or output voltages for proper voltage

levels. The POR output has a delay time that is

programmable with a capacitor from the CSET pin to

ground. The delay time can be programmed to be as

long as 1 second.

In steady-state conditions, the POR output is high if at

least one channel (LDO2 and DC-DC, LDO1) is

enabled and has reached regulation. This is equivalent

to performing a logic OR operation on the status of the

output voltages.

If any of the outputs is subsequently pulled out of

regulation (e.g., due to a momentary overload), the

POR signal goes low and it remains low as long as the

affected output is out of regulation. If the affected

output returns in regulation, POR is asserted high after

the delay time programmed with the capacitor at the

CSET pin.

The ESD protection of the POR pin is free from

clamping diodes to the input supply rails. Therefore, the

POR signal can be asserted to host I/Os under backup

power domains or pulled up to backup power sources

without the risk of parasitic leakage, even if the main

power to the MIC2800 is removed.

3.12

CSET

The CSET pin is a current source output that charges a

capacitor that sets the delay time for the Power-on

Reset output from low-to-high. The delay for POR high-

to-low (detecting an undervoltage on any of the

outputs) is always minimal. The current source of

1.25 µA charges a capacitor up from 0V. When the

capacitor reaches 1.25V, the output of the POR is

allowed to go high. The delay time in microseconds is

equal to the CSET capacitor value in picofarads.

EQUATION 3-2:

3.13

CBYP

The internal reference voltage can be bypassed with a

capacitor to ground to reduce output noise and

increase power supply rejection (PSRR). A quick-start

feature allows for quick turn on of the output voltage.

The recommended nominal bypass capacitor is 0.1 µF,

but it can be increased, which will also result in an

increase to the start-up time.

RTOP

RBOT

VOUT

VFB

------------- 1

–







PORDelay

s



CSET pF

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