MIC2800 datasheet(17/32 Pages) MICROCHIP

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DS20005839C-page 17

MIC2800

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

3.1

LOWQ

The LOWQ pin provides a logic level control between

the internal PWM mode and the low noise linear

regulator mode. With LOWQ pulled low (<0.2V),

quiescent current of the device is greatly reduced by

switching to a low noise linear regulator mode that has

a typical IQ of 20 µA (LDO2 ON only). In LowQ mode

the LDO output can deliver 60 mA of current to the

output. By placing LOWQ high (>1V), the device

transitions into a constant frequency PWM buck

regulator mode. This allows the device the ability to

efficiently deliver up to 600 mA of output current at the

same output voltage, and to support load transients

generated by processor activity.

LOWQ mode also limits the output load of both LDO1

and LDO2 to 10 mA.

The ESD protection of the LOWQ pin is free from

clamping diodes to the input supply rails, therefore the

LOWQ signal can be driven by host I/Os under backup

power domains without the risk of parasitic leakage,

even if the main power to the MIC2800 is removed.

3.2

BIAS

The BIAS pin supplies the power to the internal control

and reference circuitry. The bias is powered from AVIN

through an internal 6Ω resistor. A small 0.1 µF ceramic

capacitor is required for bypassing.

3.3

SGND

Signal ground (SGND) is the ground path for the

biasing and control circuitry. The current loop for the

signal ground should be as small as possible.

3.4

PGND

Power ground (PGND) is the ground path for the high

current PWM mode. The current loop for the power

ground should be as small as possible.

TABLE 3-1:

PIN FUNCTION TABLE

Pin Number

16-Pin QFN

Pin Name

Description

1LOWQ

LOWQ Mode. Active Low Input. Logic High = Full Power Mode; Logic Low = LOWQ

Mode; Do not leave floating.

BIAS

Internal circuit bias supply. It must be decoupled to signal ground with a 0.1 µF

capacitor and should not be loaded.

SGND

Signal ground

PGND

Power ground

Switch (Output): Internal power MOSFET output switches.

6VIN

Supply Input – DC/DC. Must be tied to PIN7 externally.

7VIN

Supply Input – LDO2. Must be tied to PIN6 externally.

LDO2

Output of LDO regulator 2.

Feedback. Input to the error amplifier for DC/DC converter. For fixed output voltages

connect directly to VOUT and an internal resistor network sets the output voltage.

LDO

LDO Output: Connect to VOUT of the DC/DC for LOWQ mode operation.

LDO1

Output of LDO regulator 1.

POR

Power-on Reset Output: Open-drain output. Active low indicates an output

undervoltage condition on either one of the three regulated outputs.

CSET

Delay Set Input: connect external capacitor to GND to set the internal delay for the

POR output. When left open, there is a minimum delay. This pin cannot be grounded.

CBYP

Reference Bypass: connect external 0.1 µF to GND to reduce output noise. May be left

open.

EN1

Enable Input (DC/DC and LDO1). Active High Input. Logic high = On; Logic low = Off;

do not leave floating.

EN2

Enable Input (LDO 2). Active High Input. Logic high = On; Logic low = Off; do not leave

floating.

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