YSS950

5

■ Comparison of Yamaha audio DSP

Chip Name

DAP1

ADAMB

EVE

Function

YSS950

YSS944

YSS943

YSS940

YSS920B

Dolby digital decoding

N

Y

N

Dolby Digital EX decoding

N

Y

N

AAC decoding

N

Y

N

PCM input playback

Y (up to 16 channels）

Y (up to 8 channels）

Y (up to 16 channels)

Dolby Pro Logic II decoding

Y

Y

N

Dolby Pro Logic IIx decoding

Y

Y

N

DTS decoding

N

Y

Y

N

N

DTS 96/24 decoding

N

Y

Y

N

N

DTS-ES decoding

N

Y

N

N

N

DTS Neo:6 decoding

N

Y

N

N

N

Tone control

Y

Y

Y

Bass management

Y

Y

Y

Volume adjustment

Y

Y

Y

Noise generation

Y

Y

Y

Impulse generation

Y

Y

Y

Dynamic range controller

Y

Y

Y

Harmonics regenerator

Y

N

N

Nch surround

Y (Mixer)

Y

Y(Channel Distributor)

Sound field

Y

Y

Y

Virtual surround

Y

Y

Y

Headphone surround

Y

Y

N

Parametric equalizer

Y (8ch x 8Band x X)

Y (8ch x 5Band)

Y (5ch x 3Band)

Graphic equalizer

Y (PEQ implementation)

Y (PEQ implementation)

Y(2ch x 10band)

Channel divider

Y

Y

Y

Automatic acoustic calibration

Y

Y

N

Down mixing

Y (Mixer)

Y

Y

Mixer

Y

N

Y

Down sampling

Y (16 channels)

Y (2 channels)

N

Modification of firmware placement

Y

N

N

Multiple firmware calls

Y

N

N

User programmability

Y (design with module)

N

Y(design with assembler)

Precision of calculations

Internal data bus:32-bit floating point (24-bit mantissa, 8-bit exponent),

Coefficient : 32-bit floating point

Internal data bus:32-bit floating point

(28-bit mantissa, 4-bit exponent),

Coefficient : 16-bit fixed point

Microcontroller interface

Four-wire serial interface

Firmware download

Y

Y

Y

Digital audio interface

24

bits

(fixed)

or

32

bits

(floating) × 16 channels,

TDM (4 channels or 8 channels)

is enabled

24 bits (fixed) ×8 channels

24 bits (fixed) or 32 bits (floating) ×

16 channels

Audio data channel switching control

Y (input and output)

Y (output)

N

Bypass

Y

Y

Y (realize by firmware)

User mute

Y (input and output)

Y (output)

Y (output)

External memory interface

N

SRAM (4Mbit)

DRAM or SRAM (4Mbit)

Input delay (lip sync)

Y

Y

Y

Output delay

Y

Y

Y

Stream detection

N

Y

N

Auto mute

Y

Y

N

Status port

Auto mute, interrupt

Zero detection, auto mute, interrupt

Zero detection, etc

General-purpose I/O ports

4

8

20

Internal operation clock generator

Y

Y

Y

Power-up/power-down

Y

Y

N

Operation frequency

165.888 MHz

178.176MHz

50MHz

Power supply voltage

1.2V (core), 3.3V (pin)

2.5V (core), 3.3V (pin)

Power consumption (Typ.)

130 mW

211mW (Dolby Digital decoding)

165mW

Package

SQFP64

LQFP144

SQFP100

Lead-free

Y

Y

Y

[Caution]

“Dolby”, “Dolby Pro Logic II”, and “Dolby Pro Logic IIx” are trademarks of Dolby Laboratories.

“DTS”, “DTS-ES”, “DTS-96/24”, and “DTS Neo:6” are trademarks of Digital Theater Systems, Inc.