RTL8305SC
Datasheet
5-port 10/100Mbps Single-Chip Dual MII Switch Controller
70
Track ID: JATR-1076-21 Rev. 1.2
7.3. PHY 2 Registers
7.3.1.
PHY 2 Register 0 for Port 2: Control
This register has the same definition as PHY 0 Register 0 for Port 0: Control, page 53.
7.3.2.
PHY 2 Register 1 for Port 2: Status
This register has the same definition as PHY 0 Register 1 for Port 0: Status, page 54.
7.3.3.
PHY 2 Register 2 for Port 2: PHY Identifier 1
This register has the same definition as PHY 0 Register 2 for Port 0: PHY Identifier 1, page 54.
7.3.4.
PHY 2 Register 3 for Port 2: PHY Identifier 2
This register has the same definition as PHY 0 Register 3 for Port 0: PHY Identifier 2, page 55.
7.3.5.
PHY 2 Register 4 for Port 2: Auto-Negotiation Advertisement
This register has the same definition as PHY 0 Register 4 for Port 0: Auto-Negotiation Advertisement,
page 55.
7.3.6.
PHY 2 Register 5 for Port 2: Auto-Negotiation Link Partner
Ability
This register has the same definition as PHY 0 Register 5 for Port 0: Auto-Negotiation Link Partner
Ability, page 56.
7.3.7.
PHY 2 Register 16~17: Internal Use Register
Table 98. PHY 2 Register 16~17: Internal Use Register
Reg.bit
Name
Mode Description
Default
16
Internal Use
RW
0xFFFF
17
Internal Use
RW
0xFFFF
7.3.8.
PHY 2 Register 18~19: Internal Use Register
Table 99. PHY 2 Register 18~19: Internal Use Register
Reg.bit
Name
Mode
Description
Default
18
Internal Use
RW
0xFFFF
19
Internal Use
RW
0xFFFF
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