HT9480 datasheet(11/47 Pages) HOLTEK

11 / 47 page

HT9480

Rev. 1.20

July 31, 2002

Once the data ready interrupt is triggered, the stack is

not full, and the EMI bit is set, a subroutine call to loca-

tion 04H will occur. The related interrupt request flag

(EIF) will, however, be reset, and the EMI bit cleared to

disable further interrupts. This interrupt should be pro-

cessed carefully if the battery fail interrupt is activated

as well.

The battery fail interrupt, on the other hand, is triggered

by a high to low transition on BAF. When the battery fail

interrupt is enabled, the stack is not full, and the interrupt

request flag (EIF; bit 4 of INTC) is set, a subroutine call

to location 04H will occur. The related interrupt request

flag (EIF) will also be reset, and the EMI bit be cleared to

disable other interrupts.

The programmable timer interrupt is automatically trig-

gered at a rate of 256Hz/N (where the value of N ranges

from 1 to 256), and then the interrupt request flag (T0F;

bit 5 of INTC) is set. When the timer interrupt is enabled,

the stack is not full, and the programmable timer inter-

rupt is activated, a subroutine call to location 08H will oc-

cur. Then, the related interrupt request flag (T0F) will be

reset, and the EMI bit cleared to disable other inter-

rupts.

The timer/event counter interrupt is initialized by setting

the timer/event counter interrupt request flag (T1F; bit 6

of INTC), which is normally caused by a timer overflow.

When the interrupt is enabled, the stack is not full, and

the T1F bit is set, a subroutine call to location 0CH will

occur. The related interrupt request flag (T1F) will be re-

set, and the EMI bit cleared to disable further interrupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are all held until the

²RETI²

instruction is executed, or the EMI bit and the related in-

terrupt control bit are both set to 1 (if the stack is not full).

To return from the interrupt subroutine, a

²RET² or

²RETI² instruction may be invoked. RETI will set the

EMI bit to enable an interrupt service, but RET will not.

The interrupts are serviced between the rising edges of

the two adjacent T2 clocks. In case of simultaneous re-

quests, the following table shows the priority that is ap-

plied. These can be masked by resetting the EMI bit.

NO.

Interrupt Source

Priority

Vector

Data ready interrupt and

battery fail interrupt

04H

Programmable timer in-

terrupt

08H

Timer/event counter over-

flow

0CH

The programmable timer interrupt request flag (T0F),

timer/event counter interrupt request flag (T1F), data

ready interrupt and battery fail interrupt request flag

(EIF), enable timer/event counter bit (ET1I), enable data

ready interrupt bit (EEI), and enable programmable

timer interrupt bit (ET0I) make up the register INTC

which is located at 0BH in the data memory. The EEI,

ET0I, ET1I, and EMI bits are all used to control the en-

able/disable status of the interrupts, preventing the re-

quested interrupt from being serviced. Once the

interrupt request flags (T0F, T1F, and EIF) are set, they

will remain in the INTC register until the interrupts are

serviced or cleared by a software instruction.

²CALL subroutine² in the interrupt subroutine should

be used. This is because interrupts often occur in an un-

predictable manner or need to be immediately serviced

in some applications. During this time, if only one stack

is left, and enabling the interrupt is not well controlled,

the operation of a

²CALL subroutine² in the interrupt ser-

vice routine is quite likely to upset the original control se-

quence.

Oscillator configuration

The system core and the pager subsystem of the

HT9480 are clocked by different oscillators. The system

oscillator can be either a crystal or an RC type. The sub-

system low power oscillator, on the other hand, is a crys-

tal type which is designed with the power on start-up

function to reduce the stabilization time of the oscillator.

This start-up function is enabled by PC2 which is initially

set high at power on reset, and should be cleared so as

to enable the low-power oscillator function. The oscilla-

tor configuration is running in the low power mode.

The system oscillator can be configured as either an RC

or crystal type of oscillator, determined by mask option.

No matter what kind of oscillator type is selected, the

signal provides a system clock. The system clock may

also be externally connected. The HALT mode stops the

system oscillator and ignores external signals to con-

serve power.

If the system oscillator is an RC type oscillator, an exter-

nal resistor between OSC1 and OSC2 is required. The

system clock is available on OSC2, which can be used

X 1

X 2

V S S

P C 2

H T 9 4 8 0

C r y s t a l c o n n e c t i o n

( L o w p o w e r m o d e c o n t r o l )

V D D

X 1

X 2

Low power oscillator

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