HT9480 datasheet(13/47 Pages) HOLTEK

13 / 47 page

HT9480

Rev. 1.20

July 31, 2002

the WDT. In the case that

²CLR WDT1² and ²CLR

WDT2

² are chosen (i.e., CLRWDR times equal two),

these two instructions should be executed to clear the

WDT; otherwise, the WDT may reset the chip due to a

time-out.

Powerdown operation

- HALT

The HALT mode is initialized by the

²HALT² instruction

and results in the following.

The system turns off. The low power oscillator, tone

generator, LCD driver, pager decoder, and WDT oscilla-

tor all keep running (if the WDT oscillator is selected).

The contents of the on chip RAM and of the registers re-

main unchanged.

The WDT and the WDT prescaler are cleared and

counted again (if the WDT clock is from the WDT oscilla-

tor).

All the I/O ports remain in their original status.

The PD flag is set but the TO flag is cleared.

The system can quit the HALT mode by an external re-

set, an interrupt, an external falling edge signal on port

A, or a WDT overflow. An external reset leads to device

initialization and the WDT overflow performs a

²warm

reset

². After the TO and PD flags are examined, the rea-

son for the chip reset is determined. The PD flag that is

cleared on power-up is set after the

²HALT² instruction

is executed. The TO flag is set when the WDT time-out

occurs, which causes a wake-up that resets only the PC

and SP, and leaves the others in their original status.

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Every bit

in port A can be independently selected to wake up the

device by mask option. Awakening from an I/O port stim-

ulation, the program resumes execution of the next in-

struction. However, if the program awakens from an

interrupt, two sequences may occur. The program will

resume execution at the next instruction if the related in-

terrupt(s) is (are) disabled or the interrupt(s) is (are) en-

abled but the stack is full. A regular interrupt response,

on the other hand, may take place if the interrupt is en-

abled and the stack is not full.

If the wake-up event(s) occurs and the wake-up results

from an interrupt acknowledge, the actual interrupt sub-

routine execution is delayed by one or more cycles. On

the other hand, if the wake-up brings about the following

instruction execution, the actual interrupt subroutine is

executed immediately after the dummy period is com-

pleted.

To minimize power consumption, the I/O pins should all

be carefully managed before entering the HALT status.

Reset

There are five ways in which a reset can occur:

· Power on reset (POR)

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

· WDT time-out reset during HALT

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a

²warm re -

set

² that just resets the PC and SP, leaving the other cir-

cuits to keep their state. Some registers remain un-

changed during other reset conditions. Most registers

are reset to the

²initial condition² when the reset condi-

tions are met. By examining the PD and TO flags, the

program can distinguish between different

²chip resets².

RESET Conditions

Power on reset

RES reset during normal operation

RES wake-up HALT

WDT time-out during normal operation

WDT wake-up HALT

Note:

²u² means ²unchanged²

8 - b i t C o u n t e r

7 - b i t C o u n t e r

W S 0 ~ W S 2

8 - t o - 1 M U X

W D T T i m e - o u t

W D T P r e s c a l e r

S y s t e m C l o c k / 4

M a s k

O p t i o n

S e l e c t

W D T C L K

Watchdog Timer

R E S

V D D

Reset circuit

HT9480 Datasheet(PDF) 13 Page - Holtek Semiconductor Inc

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