PI7C8152AMA datasheet(72/90 Pages) PERICOM

72 / 90 page

PI7C8152A & PI7C8152B

2-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 72 of 90

October 16, 2003 – Revision 1.11

12.1.15

I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch

Bit

Function

Type

Description

11:8

32-bit Indicator

R/O

Read as 01h to indicate 32-bit I/O addressing

15:12

I/O Limit

Address

[15:12]

R/W

Defines the top address of the I/O address range for the bridge to

determine when to forward I/O transactions from one interface to

the other. The upper 4 bits correspond to address bits [15:12] and

are writable. The lower 12 bits corresponding to address bits [11:0]

are assumed to be FFFh. The upper 16 bits corresponding to

address bits [31:16] are defined in the I/O limit address upper 16

bits address register

Reset to 0

12.1.16

SECONDARY STATUS REGISTER – OFFSET 1Ch

Bit

Function

Type

Description

20:16

Reserved

R/O

Reset to 0

66MHz Capable

R/O

Set to 1 to indicate PI7C8152x is capable of 66MHz operation on

the secondary interface

Reset to 1

Reserved

R/O

Reset to 0

Fast Back-to-

Back Capable

R/O

Set to 1 to indicate PI7C8152x is capable of decoding fast back-to-

back transactions on the secondary interface to different targets

Reset to 1

Data Parity Error

Detected

R/WC

Set to 1 when S_PERR_L is asserted and bit 6 of command register

is set

Reset to 0

26:25

DEVSEL_L

timing

R/O

DEVSEL# timing (medium decoding)

00: fast DEVSEL_L decoding

01: medium DEVSEL_L decoding

10: slow DEVSEL_L decoding

11: reserved

Reset to 01

Signaled Target

Abort

R/WC

Set to 1 (by a target device) whenever a target abort cycle occurs on

its secondary interface

Reset to 0

Received Target

Abort

R/WC

Set to 1 (by a master device) whenever transactions on its secondary

interface are terminated with target abort

Reset to 0

Received Master

Abort

R/WC

Set to 1 (by a master) when transactions on its secondary interface

are terminated with Master Abort

Reset to 0

Received System

Error

R/WC

Set to 1 when S_SERR_L is asserted

Reset to 0

Detected Parity

Error

R/WC

Set to 1 when address or data parity error is detected on the

secondary interface

Reset to 0

PI7C8152AMA Datasheet(PDF) 72 Page - Pericom Semiconductor Corporation

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