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PI7C8152AMA Datasheet(PDF) 73 Page - Pericom Semiconductor Corporation

Part # PI7C8152AMA
Description  2-Port PCI-to-PCI Bridge
PDF  90 Pages
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Manufacturer  PERICOM [Pericom Semiconductor Corporation]
Direct Link  http://www.pericom.com
Logo PERICOM - Pericom Semiconductor Corporation

PI7C8152AMA Datasheet(HTML) 73 Page - Pericom Semiconductor Corporation

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PI7C8152A & PI7C8152B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 73 of 90
October 16, 2003 – Revision 1.11
12.1.17
MEMORY BASE ADDRESS REGISTER – OFFSET 20h
Bit
Function
Type
Description
3:0
Reserved
R/O
Lower four bits of register are read only and return 0.
Reset to 0
15:4
Memory Base
Address [15:4]
R/W
Defines the bottom address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be 0.
Reset to 0
12.1.18
MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h
Bit
Function
Type
Description
19:16
Reserved
R/O
Lower four bits of register are read only and return 0.
Reset to 0
31:20
Memory Limit
Address [31:20]
R/W
Defines the top address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be FFFFFh.
12.1.19
PEFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET
24h
Bit
Function
Type
Description
3:0
64-bit addressing
R/O
Indicates 64-bit addressing
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 1
15:4
Prefetchable
Memory Base
Address [31:20]
R/W
Defines the bottom address of an address range for the bridge to
determine when to forward memory read and write transactions from
one interface to the other. The upper 12 bits correspond to address
bits [31:20] and are writable. The lower 20 bits are assumed to be 0.
The memory base register upper 32 bits contains the upper half of the
base address.
12.1.20
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER –
OFFSET 24h
Bit
Function
Type
Description
19:16
64-bit addressing
R/O
Indicates 64-bit addressing
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 1



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