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PI7C8152AMA Datasheet(PDF) 17 Page - Pericom Semiconductor Corporation |
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PI7C8152AMA Datasheet(HTML) 17 Page - Pericom Semiconductor Corporation |
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17 / 90 page  PI7C8152A & PI7C8152B 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Page 17 of 90 October 16, 2003 – Revision 1.11 Pin Number Name Type Pin Number Name Type Pin Number Name Type 49 S_CFN_L I 50 VSS P 51 S_CLKIN I 52 S_VIO I 53 S_CLKOUT[0] O 54 VSS P 55 S_CLKOUT[1] O 56 VDD P 57 S_CLKOUT[2] O 58 VSS P 59 S_CLKOUT[3] O 60 VDD P 61 S_CLKOUT[4] O 62 SCAN_EN I/O 63 SCAN_TM_L I 64 P_RESET_L I 65 VSS P 66 P_CLK I 67 P_VIO I 68 P_GNT_L I 69 P_REQ_L TS 70 P_AD[31] TS 71 VSS P 72 P_AD[30] TS 73 P_AD[29] TS 74 P_AD[28] TS 75 VDD P 76 P_AD[27] TS 77 P_AD[26] TS 78 P_AD[25] TS 79 P_AD[24] TS 80 VDD P 81 VSS P 82 P_CBE_L[3] TS 83 P_IDSEL I 84 P_AD[23] TS 85 P_AD[22] TS 86 VSS P 87 P_AD[21] TS 88 P_AD[20] TS 89 P_AD[19] TS 90 VDD P 91 P_AD[18] TS 92 P_AD[17] TS 93 P_AD[16] TS 94 VSS P 95 P_CBE_L[2] TS 96 P_FRAME_L STS 97 P_IRDY_L STS 98 VDD P 99 P_TRDY_L STS 100 P_DEVSEL_L STS 101 P_STOP_L STS 102 P_LOCK_L I 103 VSS P 104 P_PERR_L STS 105 P_SERR_L OD 106 P_PAR TS 107 P_CBE_L[1] TS 108 VDD P 109 P_AD[15] TS 110 P_AD[14] TS 111 P_AD[13] TS 112 VSS P 113 P_AD[12] TS 114 P_AD[11] TS 115 P_AD[10] TS 116 VDD P 117 P_AD[9] TS 118 P_AD[8] TS 119 VSS P 120 VDD P 121 VSS P 122 P_CBE_L[0] TS 123 P_AD[7] TS 124 P_AD[6] TS 125 VDD P 126 P_AD[5] TS 127 P_AD[4] TS 128 VSS P 129 P_AD[3] TS 130 P_AD[2] TS 131 VDD P 132 P_AD[1] TS 133 P_AD[0] TS 134 S_AD[0] TS 135 VSS P 136 S_AD[1] TS 137 S_AD[2] TS 138 S_AD[3] TS 139 VDD P 140 S_AD[4] TS 141 S_AD[5] TS 142 S_AD[6] TS 143 VSS P 144 S_AD[7] TS 145 S_CBE_L[0] TS 146 S_AD[8] TS 147 VDD P 148 S_AD[9] TS 149 S_AD[10] TS 150 S_AD[11] TS 151 VSS P 152 S_AD[12] TS 153 S_AD[13] TS 154 VDD P 155 S_AD[14] TS 156 S_AD[15] TS 157 VSS P 158 S_CBE_L[1] TS 159 BPCCE I 160 VDD P 3 PCI BUS OPERATION This Chapter offers information about PCI transactions, transaction forwarding across PI7C8152x, and transaction termination. The PI7C8152x has two 128-byte buffers for read data buffering of upstream and downstream transactions. Also, PI7C8152x has two 128- byte buffers for write data buffering of upstream and downstream transactions. 3.1 TYPES OF TRANSACTIONS This section provides a summary of PCI transactions performed by PI7C8152x. Table 3-1 lists the command code and name of each PCI transaction. The Master and Target columns indicate support for each transaction when PI7C8152x initiates transactions as a master, on the primary and secondary buses, and when PI7C8152x responds to transactions as a target, on the primary and secondary buses. |
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