PI7C8152AMA datasheet(20/90 Pages) PERICOM

20 / 90 page

PI7C8152A & PI7C8152B

2-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 20 of 90

October 16, 2003 – Revision 1.11

3.6.1

MEMORY WRITE TRANSACTIONS

Posted write forwarding is used for “Memory Write” and “Memory Write and Invalidate”

transactions.

When PI7C8152x determines that a memory write transaction is to be forwarded across the

bridge, PI7C8152x asserts DEVSEL_L with medium decode timing and TRDY_L in the

next cycle, provided that enough buffer space is available in the posted memory write

queue for the address and at least one DWORD of data. Under this condition, PI7C8152x

accepts write data without obtaining access to the target bus. The PI7C8152x can accept

one DWORD of write data every PCI clock cycle. That is, no target wait state is inserted.

The write data is stored in an internal posted write buffers and is subsequently delivered to

the target. The PI7C8152x continues to accept write data until one of the following events

occurs:

The initiator terminates the transaction by de-asserting FRAME_L and IRDY_L.

An internal write address boundary is reached, such as a cache line boundary or an

aligned 4KB boundary, depending on the transaction type.

The posted write data buffer fills up.

When one of the last two events occurs, the PI7C8152x returns a target disconnect to the

requesting initiator on this data phase to terminate the transaction.

Once the posted write data moves to the head of the posted data queue, PI7C8152x asserts

its request on the target bus. This can occur while PI7C8152x is still receiving data on the

initiator bus. When the grant for the target bus is received and the target bus is detected in

the idle condition, PI7C8152x asserts FRAME_L and drives the stored write address out on

the target bus. On the following cycle, PI7C8152x drives the first DWORD of write data

and continues to transfer write data until all write data corresponding to that transaction is

delivered, or until a target termination is received. As long as write data exists in the queue,

PI7C8152x can drive one DWORD of write data in each PCI clock cycle; that is, no master

wait states are inserted. If write data is flowing through PI7C8152x and the initiator stalls,

PI7C8152x will signal the last data phase for the current transaction at the target bus if the

queue empties. PI7C8152x will restart the follow-on transactions if the queue has new data.

PI7C8152x ends the transaction on the target bus when one of the following conditions is

met:

All posted write data has been delivered to the target.

The target returns a target disconnect or target retry (PI7C8152x starts another

transaction to deliver the rest of the write data).

The target returns a target abort (PI7C8152x discards remaining write data).

The master latency timer expires, and PI7C8152x no longer has the target bus grant

(PI7C8152x starts another transaction to deliver remaining write data).

Section 3.9.3.2 provides detailed information about how PI7C8152x responds to target

termination during posted write transactions.

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