PI7C8152AMA datasheet(24/90 Pages) PERICOM

24 / 90 page

PI7C8152A & PI7C8152B

2-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 24 of 90

October 16, 2003 – Revision 1.11

transactions. If these locations are mapped in memory space, use the memory read

command and map the target into non-prefetchable (memory-mapped I/O) memory space

to use non-prefetching behavior.

3.7.3

READ PREFETCH ADDRESS BOUNDARIES

PI7C8152x imposes internal read address boundaries on read prefetched data. When a read

transaction reaches one of these aligned address boundaries, the PI7C8152x stops pre-

fetched data, unless the target signals a target disconnect before the read prefetched

boundary is reached. When PI7C8152x finishes transferring this read data to the initiator, it

returns a target disconnect with the last data transfer, unless the initiator completes the

transaction before all pre-fetched read data is delivered. Any leftover prefetched data is

discarded.

Prefetchable read transactions in flow-through mode prefetch to the nearest aligned 4KB

address boundary, or until the initiator de-asserts FRAME_L. Section 3.7.6 describes flow-

through mode during read operations.

Table 3-4shows the read prefetch address boundaries for read transactions during non-

flow-through mode.

Table 3-4 READ PREFETCH ADDRESS BOUNDARIES

Type of Transaction

Address Space

Cache

Line

Size

(CLS)

Prefetch Address Boundary

Configuration Read

One DWORD (no prefetch)

I/O Read

One DWORD (no prefetch)

Memory Read

Non-Prefetchable

One DWORD (no prefetch)

Memory Read

Prefetchable

CLS = 0 or 16

16-DWORD aligned address

boundary

Memory Read

Prefetchable

CLS = 1, 2, 4, 8

Cache line address boundary

Memory Read Line

CLS = 0 or 16

16-DWORD aligned address

boundary

Memory Read Line

CLS = 1, 2, 4, 8

Cache line boundary

Memory Read Multiple

CLS = 0 or 16

Queue full

Memory Read Multiple

CLS = 1, 2, 4, 8

Second cache line boundary

- does not matter if it is prefetchable or non-prefetchable

* don’t care

Table 3-5 READ TRANSACTION PREFETCHING

Type of Transaction

Read Behavior

I/O Read

Prefetching never allowed

Configuration Read

Prefetching never allowed

Downstream: Prefetching used if address is prefetchable space

Memory Read

Upstream: Prefetching used

Memory Read Line

Prefetching always used

Memory Read Multiple

Prefetching always used

See Section 4.3 for detailed information about prefetchable and non-prefetchable address spaces.

3.7.4

DELAYED READ REQUESTS

PI7C8152x treats all read transactions as delayed read transactions, which means that the

read request from the initiator is posted into a delayed transaction queue. Read data from

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