PI7C8152AMA datasheet(80/90 Pages) PERICOM

80 / 90 page

PI7C8152A & PI7C8152B

2-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 80 of 90

October 16, 2003 – Revision 1.11

Bit

Function

Type

Description

Master Abort On

Posted Write

R/W

Controls PI7C8152x’s ability to assert P_SERR_L when it receives a

master abort when attempting to deliver posted write data.

0: P_SERR_L is asserted if this event occurs and the SERR# enable

bit in the command register is set

1: P_SERR_L is not asserted if this event occurs

Reset to 0

Delayed Write

Non-Delivery

R/W

Controls PI7C8152x’s ability to assert P_SERR# when it is unable to

transfer delayed write data after 224 attempts.

0: P_SERR_L is asserted if this event occurs and the SERR_L enable

bit in the command register is set

1: P_SERR_L is not asserted if this event occurs

Reset to 0

Delayed Read –

No Data From

Target

R/W

Controls PI7C8152x’s ability to assert P_SERR_L when it is unable

to transfer any read data from the target after 224 attempts.

0: P_SERR_L is asserted if this event occurs and the SERR_L enable

bit in the command register is set

1: P_SERR_L is not asserted if this event occurs

Reset to 0

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0

12.1.33

SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h

Bit

Function

Type

Description

1:0

S_CLKOUT[0]

disable

R/W

S_CLKOUT[0] (slot 0) Enable

00: enable S_CLKOUT[0]

01: enable S_CLKOUT[0]

10: enable S_CLKOUT[0]

11: disable S_CLKOUT[0] and driven HIGH

Reset to 00

3:2

Clock 1 disable

R/W

S_CLKOUT[1] (slot 1) Enable

00: enable S_CLKOUT[1]

01: enable S_CLKOUT[1]

10: enable S_CLKOUT[1]

11: disable S_CLKOUT[1] and driven HIGH

Reset to 00

5:4

Clock 2 disable

R/W

S_CLKOUT[2] (slot 2) Enable

00: enable S_CLKOUT[2]

01: enable S_CLKOUT[2]

10: enable S_CLKOUT[2]

11: disable S_CLKOUT[2] and driven HIGH

Reset to 00

PI7C8152AMA Datasheet(PDF) 80 Page - Pericom Semiconductor Corporation

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