PI7C8152AMA datasheet(79/90 Pages) PERICOM

79 / 90 page

PI7C8152A & PI7C8152B

2-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 79 of 90

October 16, 2003 – Revision 1.11

12.1.31

SECONDARY BUS ARBITER PREEMPTION CONTROL

Bit

Function

Type

Description

31:28

Secondary bus

arbiter

preemption

contorl

R/W

Controls the number of clock cycles after frame is asserted before

preemption is enabled.

1xxx: Preemption off

0000: Preemption enabled after 0 clock cycles after FRAME asserted

0001: Preemption enabled after 1 clock cycle after FRAME asserted

0010: Preemption enabled after 2 clock cycles after FRAME asserted

0011: Preemption enabled after 4 clock cycles after FRAME asserted

0100: Preemption enabled after 8 clock cycles after FRAME asserted

0101: Preemption enabled after 16 clock cycles after FRAME

asserted

0110: Preemption enabled after 32 clock cycles after FRAME

asserted

0111: Preemption enabled after 64 clock cycles after FRAME

asserted

12.1.32

P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h

Bit

Function

Type

Description

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0

Posted Write

Parity Error

R/W

Controls PI7C8152x’s ability to assert P_SERR_L when it is unable

to transfer any read data from the target after 224 attempts.

0: P_SERR_L is asserted if this event occurs and the SERR_L enable

bit in the command register is set.

1: P_SERR_L is not asserted if this event occurs.

Reset to 0

Posted Write

Non-Delivery

R/W

Controls PI7C8152x’s ability to assert P_SERR_L when it is unable

to transfer delayed write data after 224 attempts.

0: P_SERR_L is asserted if this event occurs and the SERR_L enable

bit in the command register is set

1: P_SERR_L is not asserted if this event occurs

Reset to 0

Target Abort

During Posted

Write

R/W

Controls PI7C8152x’s ability to assert P_SERR_L when it receives a

target abort when attempting to deliver posted write data.

0: P_SERR_L is asserted if this event occurs and the SERR_L enable

bit in the command register is set

1: P_SERR_L is not asserted if this event occurs

Reset to 0

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