AK4342EN datasheet(27/43 Pages) AKM

27 / 43 page

ASAHI KASEI

[AK4342]

MS0506-E-02

2006/07

- 27 -

System Reset

PDN pin must keep “L” until all power supply pins (AVDD, DVDD, PVDD, HVDD and TVDD) are applied. After they

are applied, PDN pin must be set to “H”. After exiting reset (PDN pin: “L”

“H”), all blocks (VCOM, DAC, HPL, HPR,

LAUX, RAUX, LOUT, ROUT and charge pump circuit) switch to the power-down state. The contents of the control

DAC exits reset and power down state by MCLK edge after PMDAC bit is changed to “1”, and then DAC is powered up

and the internal timing starts clocking by LRCK edge. DAC is in power-down mode until MCLK and LRCK are input.

Power-Up/Down Sequence

Power Supply

PDN pin

PMVCM bit

Clock Input

PVEE pin

HPL/HPR pins

(or LOUT/ROUT pins)

(4)

DAC Internal

State

Power Down

Normal Operation

PMCP bit

(1)

Power Down

(9)

PMHP bit

(or PMLO bit)

(2)

(7)

(10)

HMUTEL/R bits

(or LMUTE bit)

PVEE

Normal

MUTE

(8)

(5)

PMDAC bit

(6)

(7)

Normal

MUTE

(9)

(6)

(8)

Don’t care

LOUT/ROUT pins

(or HPL/HPR pins)

PMLO bit

(or PMHP bit)

LMUTE bit

(or HMUTEL/R bit)

(3)

Figure 20. Example of Power-up/down Sequence

(1) After Power Up: PDN pin “L”

“H”

“L” time (1) of 150ns or more is needed to reset the AK4342.

PDN pin must keep “L” until all power supply pins (AVDD, DVDD, PVDD, HVDD and TVDD) are applied.

After they are applied, PDN pin must be set to “H”.

(2) DFS1-0, DIF2-0, DEM1-0, FS3-0, PTS1-0, STS1-0, PUT1-0, LRP, BCKP and DACLR bits should be set during this

period before the DAC and charge pump circuit are powered-up.

(3) Supply the external clocks (MCLK, BICK, LRCK)

AK4342EN Datasheet(PDF) 27 Page - Asahi Kasei Microsystems

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