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AK4342EN Datasheet(PDF) 12 Page - Asahi Kasei Microsystems |
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AK4342EN Datasheet(HTML) 12 Page - Asahi Kasei Microsystems |
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12 / 43 page ![]() ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 12 - SWITCHING CHARACTERISTICS (Continued) (Ta=25 °C; AVDD, DVDD, HVDD, PVDD=2.7 ∼ 3.6V; TVDD=2.7 ∼ 3.6V) Parameter Symbol min typ max Units Control Interface Timing (I 2C Bus mode): (Note 29) SCL Clock Frequency fSCL - - 400 kHz Bus Free Time Between Transmissions tBUF 1.3 - - µs Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 - - µs Clock Low Time tLOW 1.3 - - µs Clock High Time tHIGH 0.6 - - µs Setup Time for Repeated Start Condition tSU:STA 0.6 - - µs SDA Hold Time from SCL Falling (Note 30) tHD:DAT 0 - µs SDA Setup Time from SCL Rising tSU:DAT 0.1 - - µs Rise Time of Both SDA and SCL Lines tR - - 0.3 µs Fall Time of Both SDA and SCL Lines tF - - 0.3 µs Setup Time for Stop Condition tSU:STO 0.6 - - µs Capacitive load on bus Cb - 400 pF Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 - 50 ns Note 29. I 2C is a registered trademark of Philips Semiconductors. TVDD voltage must be 2.7V ∼ 3.6V in I2C mode. Note 30. Data must be held long enough to bridge the 300ns-transition time of SCL. |
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