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AK4342EN Datasheet(PDF) 33 Page - Asahi Kasei Microsystems |
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AK4342EN Datasheet(HTML) 33 Page - Asahi Kasei Microsystems |
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33 / 43 page  ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 33 - Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 0 0 PMAUX PMLO PMCP PMHP PMDAC PMVCM 01H Mode Control 0 AMUTE SMUTE AVCMN DIF2 DIF1 DIF0 DFS1 DFS0 02H Mode Control 1 0 0 FS3 FS2 FS1 FS0 DEM1 DEM0 03H Mode Control 2 PGAC PTS1 PTS0 STS1 STS0 DATTC BCKP LRP 04H HP Lch PGA Control 0 0 HMUTEL PGAL4 PGAL3 PGAL2 PGAL1 PGAL0 05H HP Rch PGA Control 0 0 HMUTER PGAR4 PGAR3 PGAR2 PGAR1 PGAR0 06H Output Select PUT1 PUT0 RINR RINL LINR LINL DACLR 0 07H Lineout PGA control 0 0 LMUTE LPGA4 LPGA3 LPGA2 LPGA1 LPGA0 08H DAC Lch ATT ATTL7 ATTL6 ATTL5 ATTL4 ATTL3 ATTL2 ATTL1 ATTL0 09H DAC Rch ATT ATTR7 ATTR6 ATTR5 ATTR4 ATTR3 ATTR2 ATTR1 ATTR0 All registers inhibit writing at PDN pin = “L”. PDN pin = “L” resets the registers to their default values. Note 31: The bits indicated to “0” in the register map must contain a “0” value. Note 32: Only write to address 00H to 09H. |
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