AK4342EN datasheet(39/43 Pages) AKM

39 / 43 page

ASAHI KASEI

[AK4342]

MS0506-E-02

2006/07

- 39 -

SYSTEM DESIGN

Figure 32 shows the system connection diagram. An evaluation board [AKD4342] is available which demonstrates the

optimum layout, power supply arrangements and measurement results.

MUTET

VCOM

AVDD

AVSS

DVSS

DVDD

TVDD

I2C

HPR

HPL

HVEE

PVEE

PVSS

PVDD

AK4342EN

Top View

Power Supply

2.7

∼ 3.6V

0.1u

DSP

µP

Analog Input

Lineout

Analog Ground

Digital Ground

2.2u

Headphone

0.1u

10u

10u 0.1u

Aux-out

Power Supply

1.6

∼ 3.6V

2.2u

0.1u

2.2u

(+):Note

Figure 32. Typical Connection Diagram in 3-wire mode

Note:

A 2

Ω resistor should be added in series between HVDD/PVDD pins and power supply line in

order to limit the current.

These capacitors should use low ESR (Equivalent Series Resistance) over all temperature range. When these

capacitors are not bipolar, the positive side should be connected CP pin or analog ground.

AVSS, DVSS, PVSS and HVSS of the AK4342 should be distributed separately from the ground of external

controllers.

All digital input except for pull-up pins should not be left floating.

If TVDD voltage is the same as DVDD voltage, TVDD pin is directly connected to DVDD pin and the capacitor

(10

µF and 0.1µF) connected to TVDD pin can be removed.

AK4342EN Datasheet(PDF) 39 Page - Asahi Kasei Microsystems

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