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AK4342EN Datasheet(PDF) 11 Page - Asahi Kasei Microsystems |
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AK4342EN Datasheet(HTML) 11 Page - Asahi Kasei Microsystems |
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11 / 43 page  ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 11 - SWITCHING CHARACTERISTICS (Ta=25 °C; AVDD, DVDD, HVDD, PVDD=2.7 ∼ 3.6V; TVDD=1.6 ∼ 3.6V) Parameter Symbol min typ max Units Master Clock Timing (2.7V ≤ TVDD ≤ 3.6V) Half Speed Mode (512/768fs) Normal Speed Mode (256/384/512/768fs) Double Speed Mode (128/192/256/384fs) fCLK fCLK fCLK 4.096 2.048 6.144 18.432 36.864 36.864 MHz MHz MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns Master Clock Timing (1.6V ≤ TVDD < 2.7V) Half Speed Mode (512/768fs) Normal Speed Mode (256/384fs) Double Speed Mode (128/192fs) fCLK fCLK fCLK 4.096 2.048 6.144 18.432 18.432 18.432 MHz MHz MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns LRCK Timing Frequency Half Speed Mode (DFS1-0 bits = “10”) Normal Speed Mode (DFS1-0 bits = “00”) Double Speed Mode (DFS1-0 bits = “01”) fsh fsn fsd 8 8 60 24 48 96 kHz kHz kHz Duty Cycle Duty 45 - 55 % Serial Interface Timing (Note 25) BICK Period Half Speed Mode tBCK 1/128fsh - - ns Normal Speed Mode tBCK 1/128fsn - - ns Double Speed Mode tBCK 1/64fsd - - ns BICK Pulse Width Low tBCKL 70 - - ns Pulse Width High tBCKH 70 - - ns LRCK Edge to BICK “ ↑” (Note 26) tLRB 40 - - ns BICK “ ↑” to LRCK Edge (Note 26) tBLR 40 - - ns LRCK Edge to BICK “ ↓” (Note 27) tLRB 40 - - ns BICK “ ↓” to LRCK Edge (Note 27) tBLR 40 - - ns SDATA Hold Time tSDH 40 - - ns SDATA Setup Time tSDS 40 - - ns Control Interface Timing (3-wire Serial mode) CCLK Period tCCK 200 - - ns CCLK Pulse Width Low tCCKL 80 - - ns Pulse Width High tCCKH 80 - - ns CDTI Setup Time tCDS 40 - - ns CDTI Hold Time tCDH 40 - - ns CSN “H” Time tCSW 150 - - ns CSN “ ↓” to CCLK “↑” tCSS 50 - - ns CCLK “ ↑” to CSN “↑” tCSH 50 - - ns Power-down & Reset Timing PDN Pulse Width (Note 28) tPD 150 - - ns Note 25. Refer to “Serial Data Interface”. Note 26. When BCKP bit is set to “0”, BICK rising edge must not occur at the same time as LRCK edge. Note 27. When BCKP bit is set to “1”, BICK falling edge must not occur at the same time as LRCK edge. Note 28. The AK4342 can be reset by bringing PDN pin = “L” to “H” only upon power up. |
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