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GL826 Datasheet(PDF) 30 Page - GENESYS LOGIC

Part # GL826
Description  USB 2.0 Multi-Slot Flash Card Reader Controller (All-in-one with Dual SD/MMC bus Interface)
PDF  43 Pages
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Manufacturer  GENESYS [GENESYS LOGIC]
Direct Link  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL826 Datasheet(HTML) 30 Page - GENESYS LOGIC

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GL826 USB 2.0 Multi-Slot Flash Card Reader Controller
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 30
Table 4.5－
－
－
－AC Characteristics of Smart Media Interface (CL = 40 pF)
Symbol
Parameter
Min.
Max.
Unit
tCLS
CLE Setup Time
20
-
ns
tCLH
CLE Hold Time
40
-
ns
tCS
-CE Setup Time
20
-
ns
tCH
-CE Hold Time
40
-
ns
tWP
-WE Pulse Width
40
-
ns
tALS
ALE Setup Time
20
-
ns
tALH
ALE Hold Time
40
-
ns
tDS
Data Setup Time
30
-
ns
tDH
Data Hold Time
20
-
ns
tWC
Write Cycle Time
80
-
ns
tWH
-WE High Hold Time
20
-
ns
tWW
-WP High to –WE Low
100
-
ns
tRR
Ready to –RE Low
20
-
ns
tRP
Read Pulse Width
60
-
ns
tRC
Read cycle Time
80
-
ns
tREA
-RE Access Time (Serial Data Access)
-
45
ns
tCEH
-CE High Hold Time (At the Last Serial Read)
250
-
ns
tREAID
-RE Access Time (ID Read)
-
90
ns
tRHZ
-RE High to Output Hi-Z
5
30
ns
tCHZ
-CE High to Output Hi-Z
-
30
ns
tREH
-RE High Hold Time
20
-
ns
tRSTO
-RE Access Time
-
45
ns
tCSTO
-CE Access Time
-
55
ns
tRHW
-RE High to -WE Low
0
-
ns
tWHC
-WE High to –CE Low
50
-
ns
tWHR
-WE High to –RE Low
60
-
ns
tAR1
ALE Low to –RE Low (Address Register Read, ID Read)
200
-
ns
tCR
-CE Low to –RE Low (Data Register Read, ID Read)
200
-
ns
tWB
-WE High to Busy
-
200
ns
tAR2
ALE Low to RE Low (Read Cycle)
150
ns
tRB
Last –RE High to Busy (at Sequential Read)
-
500
ns
tCRY
-CE High to Ready
-
1
µs



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