ADF4157 datasheet(17/20 Pages) AD

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ADF4157

Rev. 0 | Page 17 of 20

APPLICATIONS INFORMATION

INITIALIZATION SEQUENCE

After powering up the part, this programming sequence must

be followed:

Test Register (R4)

Function Register (R3)

R Divider Register (R2)

LSB FRAC Register (R1)

FRAC/INT Register (R0)

RF SYNTHESIZER: A WORKED EXAMPLE

The following equation governs how the synthesizer should be

programmed:

RFOUT = [N + (FRAC/225)] × [fPFD]

(3)

where:

RFOUT is the RF frequency output.

N is the integer division factor.

FRAC is the fractionality.

fPFD = REFIN × [(1 + D)/(R × (1 + T))]

(4)

where:

REFIN is the reference frequency input.

D is the RF REFIN doubler bit.

R is the RF reference division factor.

T is the reference divide-by-2 bit (0 or 1).

For example, in a system where a 5.8002 GHz RF frequency

output (RFOUT) is required and a 10 MHz reference frequency

input (REFIN) is available, the frequency resolution is

fRES = REFIN/225

fRES = 10 MHz/225 = 0.298 Hz

From Equation 4,

fPFD = [10 MHz × (1 + 0)/1] = 10 MHz

5.8002 GHz = 10 MHz × (N + FRAC/225)

Calculating N and FRAC values,

N = int(RFOUT/fPFD) = 580

FRAC = FMSB × 213 + FLSB

FMSB = int(((RFOUT/fPFD) − N) × 212) = 81

FLSB = int(((((RFOUT/fPFD) − N) × 212) − FMSB) × 213) = 7537

where:

FMSB is the 12-bit MSB FRAC value in Register R0.

FLSB is the 13-bit LSB FRAC value in Register R1.

int() makes an integer of the argument in brackets.

REFERENCE DOUBLER AND REFERENCE DIVIDER

The reference doubler on-chip allows the input reference signal

to be doubled. This is useful for increasing the PFD comparison

frequency. Making the PFD frequency higher improves the noise

performance of the system. Doubling the PFD frequency

usually improves noise performance by 3 dB. It is important to

note that the PFD cannot be operated above 32 MHz due to

a limitation in the speed of the Σ-Δ circuit of the N divider.

CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES

In fast-locking applications, a wide loop filter bandwidth is

required for fast frequency acquisition, resulting in increased

integrated phase noise and reduced spur attenuation. Using

cycle slip reduction, the loop bandwidth can be kept narrow to

reduce integrated phase noise and attenuate spurs while still

realizing fast lock times.

Cycle Slips

Cycle slips occur in integer-N/fractional-N synthesizers when

the loop bandwidth is narrow compared to the PFD frequency.

The phase error at the PFD inputs accumulates too fast for the PLL

to correct, and the charge pump temporarily pumps in the wrong

direction, slowing down the lock time dramatically. The ADF4157

contains a cycle slip reduction circuit to extend the linear range

of the PFD, allowing faster lock times without loop filter changes.

When the ADF4157 detects that a cycle slip is about to occur, it

turns on an extra charge pump current cell. This outputs a constant

current to the loop filter or removes a constant current from the

loop filter (depending on whether the VCO tuning voltage needs

to increase or decrease to acquire the new frequency). The effect is

that the linear range of the PFD is increased. Stability is main-

tained because the current is constant and is not a pulsed current.

If the phase error increases again to a point where another cycle

slip is likely, the ADF4157 turns on another charge pump cell.

This continues until the ADF4157 detects that the VCO

frequency has gone past the desired frequency. It then begins to

turn off the extra charge pump cells one by one until they are all

turned off and the frequency is settled.

Up to seven extra charge pump cells can be turned on. In most

applications, it is enough to eliminate cycle slips altogether,

giving much faster lock times.

Setting Bit DB28 in the R Divider register (R2) to 1 enables

cycle slip reduction. Note that a 45% to 55% duty cycle is

needed on the signal at the PFD in order for CSR to operate

correctly. The reference divide-by-2 flip-flop can help to

provide a 50% duty cycle at the PFD. For example, if a 100 MHz

reference frequency is available, and the user wants to run the

PFD at 10 MHz, setting the R divide factor to 10 results in a 10

MHz PFD signal that is not 50% duty cycle. By setting the R

divide factor to 5 and enabling the reference divide-by-2 bit, a

50% duty cycle 10 MHz signal can be achieved.

Note that the cycle slip reduction feature can only be operated

when the phase detector polarity setting is positive (DB6 in

set to negative.

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