ADF4157

Rev. 0 | Page 2 of 20

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 4

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

Circuit Description........................................................................... 8

Reference Input Section............................................................... 8

RF Input Stage............................................................................... 8

RF INT Divider............................................................................. 8

25-Bit Fixed Modulus .................................................................. 8

INT, FRAC, and R Relationship ................................................. 8

RF R Counter ................................................................................ 8

Phase Frequency Detector (PFD) and Charge Pump.............. 9

MUXOUT and LOCK Detect..................................................... 9

Input Shift Registers......................................................................9

Program Modes .............................................................................9

Register Maps.................................................................................. 10

FRAC/INT Register (R0) Map.................................................. 11

LSB FRAC Register (R1) Map .................................................. 12

R Divider Register (R2) Map .................................................... 13

Function Register (R3) Map ..................................................... 15

Test Register (R4) Map .............................................................. 16

Applications Information .............................................................. 17

Initialization Sequence .............................................................. 17

RF Synthesizer: A Worked Example ........................................ 17

Reference Doubler and Reference Divider ............................. 17

Cycle Slip Reduction for Faster Lock Times........................... 17

Spur Mechanisms ....................................................................... 18

Low Frequency Applications .................................................... 18

Filter Design—ADIsimPLL....................................................... 18

Interfacing ................................................................................... 18

PCB Design Guidelines for the Chip Scale Package.............. 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

REVISION HISTORY

7/07—Revision 0: Initial Revision