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Data Sheet

ADAQ4216

SERIAL INTERFACE

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Rev. 0 | 39 of 61

The ADAQ4216 supports a multilane SPI serial digital interface with

a common bit clock (SCK). The flexible VIO pins supply allows

the ADAQ4216 to communicate with any digital logic operating

between 1.2V and 1.8V. However, for the VIO pins levels less than

1.4V, the IO2X bit in the output driver register must be set to 1 (for

more details, see the Output Driver Register section). The serial

output data is clocked out on up to 4 SDO lanes (see Figure 102).

An echo clock mode that is synchronous with the output data is

available to ease timing requirements when using isolation on the

digital interface. A host clock mode is also available and uses an

internal oscillator to clock out the data bits. The SPI Clocking Mode,

Echo Clock Mode, Host Clock Mode, Single-Data Rate Mode,

Dual-Data Rate Mode, 1-Lane Output Data Clocking Mode, 2-Lane

Output Data Clocking Mode, 4-Lane Output Data Clocking Mode,

and Data Output Modes Summary sections describe the operation

of the ADAQ4216 SPI.

Figure 102. ADAQ4216 Multilane SPI

SPI SIGNALS

The SPI is a multilane interface that is used to both configure the

ADC as well as retrieve sampled data. It consists of the following

signals:

►

CS (input) (chip select). CS must be set to low to initiate and

enable a data transfer to or from the SDI pins or SDOx pins of

the ADC. CS timing for reading sample data can be moderated

by observing the state of the BUSY pin. For echo clock mode

and host clock mode, CS timing must be controlled by the host

processor because the BUSY_SCKOUT pin is used as the bit

clock output for these clocking modes.

►

SDI (input). Serial data input stream from the host controller to

the ADC. The SDI signal is only used when writing data into one

of the user registers of the ADAQ4216.

►

CNV (input). The CNV signal is sourced by the host controller

and initiates a sample conversion. The frequency of the CNV

signal determines the sampling rate of the ADAQ4216. The

maximum frequency of the CNV clock is 2MSPS.

►

SCK (input). Serial data clock sourced by the host controller.

The maximum SCK rate supported for output data transfer is

100MHz. For register reads and writes, the maximum SCK rate

is 86MHz for the VIO pins > 1.71V, and 81MHz for 1.14V ≤ the

VIO pins < 1.71V.

►

SDO0 through SDO3 (outputs). Data lanes to the host controller.

The number of active data lanes can be either 1-lane, 2-lane, or

4-lane (see Table 14). The number of data lanes is configured in

the Modes Register section.

►

BUSY_SCKOUT (output). The behavior of the BUSY_SCKOUT

pin is dependent on the selected clocking mode. Table 13 de-

fines the behavior of the BUSY_SCKOUT pin for each clocking

mode.

Table 13. BUSY_SCKOUT Pin Behavior vs. Clocking Mode

Clocking Mode

Behavior

SPI Clocking Mode

Valid BUSY_SCKOUT pin signal for the ADC

conversion status. The busy signal on the

BUSY_SCKOUT pin goes high when a conversion is

triggered by the CNV signal. The busy signal on the

BUSY_SCKOUT pin goes low when the conversion is

complete.

Echo Clock Mode

Bit clock. The BUSY_SCKOUT pin is a delayed version

of SCK input.

Host Clock Mode

Bit clock. The BUSY_SCKOUT pin sources the clock

signal from the internal oscillator.

The ADAQ4216 offers programmable user registers that are used

to configure the device, as shown in the Registers section. By

default, at power-up, the device is in conversion mode. Therefore,

to access the user registers, a special access command must be

sent by the host controller over the SPI, as shown in Figure 5.

When this register access command is sent over the SPI, the

device enters the register configuration mode. To readback the

values from one of the user registers listed in the Registers section,

the host controller must send the pattern shown in Figure 4. To

write to one of the user registers, the host controller must send

the pattern shown in Figure 3. In either case (read/write), the host

controller must always issue 24 clock pulses on SCK line and pull

CS low for the entire transaction.

After writing to/reading from the appropriate user registers, the host

controller must exit the register configuration mode by writing 0x01

to register address 0x0014 as detailed in the EXIT Configuration

Mode Register section. An algorithm for register read/write access

is as follows:

1. Perform a readback from a dummy register address 0x3FFF, to

enter the register configuration mode.

2. Readback from or write to the required user register addresses.

3. Exit the register configuration mode by writing 0x01 to register

address 0x0014. Exiting register configuration mode causes the

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