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Data Sheet

ADAQ4216

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

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Rev. 0 | 14 of 61

Table 11. Pin Function Descriptions (Continued)

Pin Number

Mnemonic

Type1

Description

D17, E17

VIO

Input/Output Interface Digital Power. Nominally, this pin is at the same supply as the host interface (1.8V,

1.5V, or 1.2V). This pin has a 0.2μF bypass capacitor inside the package. For VIO < 1.4V, Bit IO2X of the

output driver register must be set to 1.

PGIA Gain-Control Logic Input 1.

PGIA Gain-Control Logic Input 0.

E6, F6

VDD_FDA

FDA Positive Power Supply. This pin has a 0.1μF bypass capacitor inside the package. Bypass this pin

to GND with at least 2.2μF (0402, X5R) ceramic capacitor.

OUTP

Positive FDA Output.

E10

ADCP

Positive ADC Input.

E15 to E16, F15, G15, H15 to

H16, J15, K15, L17

IOGND

VIO Ground. Connect to the same ground plane as all GND pins.

OUTN

Negative FDA Output.

F10

ADCN

Negative ADC Input.

F16

SDO3

Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.

F17

SDO1

Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.

G7, G11 to G12, H11 to H12

DNC

Do Not Connect.

G16

SDO2

Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.

G17

SDO0

Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.

PDB_FDA

Power-Down FDA. Active low. Connect the PDB_FDA pin to GND to power down the FDA. Otherwise,

connect the PDB_FDA pin to VDD_FDA logic high supply.

H17

BUSY_SCKOUT

BUSY Indicator in SPI Clocking Mode. This pin goes high at the start of a new conversion and returns

low when the conversion finishes. Logic levels are determined by the VIO pin. When SCKOUT is

enabled, this pin function is either an echo of the incoming SCK from the host controller or a clock

sourced by the internal oscillator.

J6, K6

VSS_FDA

FDA Negative Supply. This pin has a 0.1μF bypass capacitor inside the package. Bypass this pin to

GND with at least 2.2μF (0402, X5R) ceramic capacitor. Connect to GND for fewer power supply rails.

A13 to A15, B13 to B15, J10,

K10

NIC

Not Internally Connected. These pins are not connected internally.

J16 to J17, K16 to K17

DNC

Do Not Connect. These pins are internally connected to digital output drivers in high-Z mode.

K12, L12

VDD_1.8V

LDO Voltage Output. The output is typically at 1.8V. This pin has a 1μF and 0.1μF bypass capacitors

inside the package.

EN_LDO

Enable LDO pin. For automatic start-up, connect EN_LDO to VLDO.

VLDO

Internal LDO Input Supply. This pin has a 1μF bypass capacitor inside the package. The input range for

VLDO is 2.2V to 5.5V.

L14

CSB

Chip Select Input (Active Low).

L15

SDI

Serial Data Input.

L16

SCK

Serial-Data Clock Input. When the device is selected (CSB = low), the conversion result is shifted out by

this clock.

1 AI is analog input, AO is analog output, P is power, DI is digital input, and DO is digital output.

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