Data Sheet

ADAQ4216

SPECIFICATIONS

analog.com

Rev. 0 | 7 of 61

Table 1. Specifications (Continued)

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

VIO6

1.14

1.89

V

VLDO

2.2

5.4

5.5

V

Standby Current

Inputs grounded

VDDH

8

mA

VSSH

−9

mA

VDD_FDA

4.8

mA

VSS_FDA

−3.5

mA

VDD_5V

525

µA

VIO

<1

µA

VLDO

108

µA

Shutdown Current

Inputs grounded

VDD_FDA

PDB_FDA = 0V

32

µA

VSS_FDA

PDB_FDA = 0V

−25.2

µA

VDD_5V

ADC in shutdown mode

5

µA

VIO

<1

µA

VLDO

EN_LDO = 0V, ADC in shutdown mode

0.8

µA

Operating Current

2MSPS, Input = −0.5dBFS

VDDH

VDDH = +18V

10

mA

VSSH

VSSH = −18V

−9.8

mA

VDD_5V

VDD_5V = 5.4V

2.5

3.2

mA

VDD_FDA

VDD_FDA = 5.4V

5.6

7.5

mA

VSS_FDA

VSS_FDA = 0V

−7.5

−5.6

mA

VIO

VIO = 1.8V, 1-lane SDO

0.8

mA

VLDO

VLDO = 5.4V

8

10.5

mA

Power Dissipation

2MSPS

445

mW

tRESET_DELAY

After power-on, delay from VDD_5V and

VDD_1.8V valid to RST assertion

3

ms

tRESET_PW

RST pulse width

50

ns

TEMPERATURE RANGE

Specified Performance

TMIN to TMAX

−40

+105

°C

1 These specification are not production tested but are supported by characterization data during initial product release.

2 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2MSPS.

3 See the low frequency noise plot in Figure 63. 1/f noise is canceled internally by auto-zeroing. Noise spectral density is substantially uniform from DC to fS/2.

4 Drop-out voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage.

5 Start-up time is defined as the time between the rising edge of EN_LDO to VDD_1.8V being at 90% of its nominal value.

6 When VIO < 1.4 V, Bit IO2X must be set to 1. For more details, see the Output Driver Register section.

TIMING SPECIFICATIONS

VDDH = 18V, VSSH = −18V, VDD_FDA = 5.4V, VSS_FDA = 0V, VDD_5V = 5.4V, VLDO = 5.4V, VIO = 1.8V, REFIN = 5V, fS = 2MSPS and all

specifications are TMIN to TMAX, unless otherwise noted. For the timing voltage levels, see Figure 2. For VIO < 1.4V, Bit IO2X must be set to 1.

Table 2. Digital Timing Interface

Parameter1

Symbol

Min

Typ

Max

Unit

Conversion Time: CNV Rising Edge to Data Available

tCONV

264

282

300

ns

Acquisition Phase2

tACQ

244

260

275

ns

Time Between Conversions

tCYC

500

ns

CNV High Time

tCNVH

10

ns