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ADAQ4216BBCZ Datasheet(PDF) 52 Page - Analog Devices

Part # ADAQ4216BBCZ
Description  16-Bit, 2MSPS, μModule Data-Acquisition Solution
PDF  61 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADAQ4216BBCZ Datasheet(HTML) 52 Page - Analog Devices

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Data Sheet
ADAQ4216
REGISTER DETAILS
analog.com
Rev. 0 | 52 of 61
INTERFACE CONFIGURATION A REGISTER
Address: 0x00, Reset: 0x10, Name: INTERFACE_CONFIG_A
Interface configuration settings.
Table 17. Bit Descriptions for INTERFACE_CONFIG_A
Bits
Bit Name
Description
Reset
Access
7
SW_RESET
One of two of SW_RESET bits. This bit appears in two locations in this register. Both locations must be
written at the same time to trigger a software reset of the part. All registers except for this register are reset
to their default values.
0x0
R/W
6
RESERVED
Reserved.
0x0
R
5
ADDR_ASCENSION
Determines sequential addressing behavior.
0x0
R
0: Address accessed is decremented by one for each data byte when streaming.
1: Not a valid option.
4
SDO_ENABLE
SDO Pin Enable.
0x1
R
[3:1]
RESERVED
Reserved.
0x0
R
0
SW_RESETX
Two of two of SW_RESET bits. This bit appears in two locations in this register. Both locations must be
written at the same time to trigger a software reset of the part. All registers except for this register are reset
to their default values.
0x0
R/W
INTERFACE CONFIGURATION B REGISTER
Address: 0x01, Reset: 0x00, Name: INTERFACE_CONFIG_B
Additional interface configuration settings.
Table 18. Bit Descriptions for INTERFACE_CONFIG_B
Bits
Bit Name
Description
Reset
Access
7
SINGLE_INST
Select streaming or single instruction mode.
0x0
R/W
0: Streaming mode is enabled. The address decrements as successive data bytes are received.
1: Single instruction mode is enabled.
6
STALLING
Reserved for Stalling Feature.
0x0
R/W
[5:4]
RESERVED
Reserved.
0x0
R
3
SHORT_INSTRUCTION
Set the instruction phase address to 7 bits or 15 bits.
0x0
R
0: 15-bit addressing.
1: 7-bit addressing.
[2:0]
RESERVED
Reserved.
0x0
R



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