Data Sheet

ADAQ4216

SPECIFICATIONS

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Rev. 0 | 8 of 61

Table 2. Digital Timing Interface (Continued)

Parameter1

Symbol

Min

Typ

Max

Unit

CNV Low Time

tCNVL

20

ns

Internal Oscillator Frequency

fOSC

75.1

80

84.7

MHz

1 Timing specifications assume a 5pF load capacitance on digital output pins. tCONV, tCYC, tSCK, and tSCKOUT are production tested. All other timing specifications are

guaranteed by characterization and design.

2 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2MSPS.

Figure 2. Voltage Levels for Timing

Table 3. Register Read/Write Timing

Parameter

Symbol

Min

Typ

Max

Unit

CS Pulse Width

tCSPW

10

ns

SCK Period

tSCK

VIO > 1.71V

11.6

ns

VIO > 1.14V

12.3

ns

SCK Low Time

tSCKL

5.2

ns

SCK High Time

tSCKH

5.2

ns

SCK Falling Edge to Data Remains Valid

tHSDO

2.1

ns

SCK Falling Edge to Data Valid Delay

tDSDO

VIO > 1.71V

9.4

ns

VIO > 1.14V

11.8

ns

CS Rising Edge to SDO High Impedance

tCSDIS

9

ns

SDI Valid Setup Time to SCK Rising Edge

tSSDI

1.5

ns

SDI Valid Hold Time from SCK Rising Edge

tHSDI

1.5

ns

CS Falling Edge to First SCK Rising Edge

tCSSCK

VIO > 1.71V

11.6

ns

VIO > 1.14V

12.3

ns

Last SCK Edge to CS Rising Edge

tSCKCS

5.2

ns

Figure 3. Register Configuration Mode Write Timing