AD6655 datasheet(49/84 Pages) AD

49 / 84 page

AD6655

Rev. 0 | Page 49 of 84

CONFIGURATION WITHOUT THE SPI

In applications that do not interface to the SPI control registers,

the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin,

and the SMI SCLK/PDWN pin serve as standalone CMOS-

compatible control pins. When the device is powered up, it is

assumed that the user intends to use the pins as static control

lines for the duty cycle stabilizer, output data format, output

enable, and power-down feature control. In this mode, the CSB

chip select should be connected to AVDD, which disables the

serial port interface.

Table 27. Mode Selection

External

Voltage

Configuration

AVDD (default)

Duty cycle stabilizer

enabled

SDIO/DCS

AGND

Duty cycle stabilizer

disabled

AVDD

Twos complement

enabled

SCLK/DFS

AGND (default)

Offset binary enabled

AVDD

Outputs in high

impedance

SMI SDO/OEB

AGND (default)

Outputs enabled

AVDD

Chip in power-down or

standby

SMI SCLK/PDWN

AGND (default)

Normal operation

SPI ACCESSIBLE FEATURES

Table 28 provides a brief description of the general features that

are accessible via the SPI. These features are described in detail

in Application Note AN-877, Interfacing to High Speed ADCs via

SPI (see www.analog.com). The AD6655 part-specific features

are described in the Memory Map Register Description section.

Table 28. Features Accessible Using the SPI

Feature Name

Description

Mode

Allows the user to set either power-down mode

or standby mode

Clock

Allows the user to access the DCS via the SPI

Offset

Allows the user to digitally adjust the

converter offset

Test I/O

Allows the user to set test modes to have

known data on output bits

Output Mode

Allows the user to set up outputs

Output Phase

Allows the user to set the output clock polarity

Output Delay

Allows the user to vary the DCO delay

VREF

Allows the user to set the reference voltage

DON’T CARE

SDIO

SCLK

CSB

tDH

tCLK

tDS

R/W

A12

A11

A10

tLOW

tHIGH

Figure 81. Serial Port Interface Timing Diagram

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