AD6655 datasheet(56/84 Pages) AD

56 / 84 page

AD6655

Rev. 0 | Page 56 of 84

Digital Filter Control (Register 0x103)

Bits[7:4]—Reserved

Bit 3—Half-Band Decimation Phase

When set high, Bit 3 uses the alternate phase of the decimating

half-band filter.

Bit 2—Spectral Reversal

Bit 2 enables the spectral reversal feature of the half-band filter.

Bit 1—High-Pass/Low-Pass Select

Bit 1 enables the high-pass mode of the half-band filter when

set high. Setting this bit low enables the low-pass mode (default).

Bit 0—Reserved

Bit 0 reads back as a 1.

Fast Detect Control (Register 0x104)

Bits[7:4]—Reserved

Bits[3:1]—Fast Detect Mode Select

Bits[3:1] set the mode of the fast detect output bits according to

Table 29.

Bit 0—Fast Detect Enable

Bit 0 is used to enable the fast detect output pins. When the FD

outputs are disabled, the outputs go into a high impedance state.

In LVDS mode when the outputs are interleaved, the outputs go

high-Z only if both channels are turned off (power-down/

standby/output disabled). If only one channel is turned off

(power-down/standby/output disabled), the fast detect outputs

repeat the data of the active channel.

Coarse Upper Threshold (Register 0x105)

Bits[7:3]—Reserved

Bits[2:0]—Coarse Upper Threshold

These bits set the level required to assert the coarse upper

threshold indication (see Table 25).

Fine Upper Threshold (Register 0x106 and Register 0x107)

These registers provide a fine upper limit threshold. The 13-bit

value is compared to the 13-bit magnitude from the ADC block.

If the ADC magnitude exceeds this threshold value, the F_UT

indicator is set.

Fine Lower Threshold (Register 0x108 and Register 0x109)

These registers provide a fine lower limit threshold. This 13-bit

value is compared with the 13-bit magnitude from the ADC

block. If the ADC magnitude is less than this threshold value,

the F_LT indicator is set.

Increase Gain Dwell Time (Register 0x10A and

Bits[15:8]

Bits[7:0]

These register values set the minimum time in ADC sample

clock cycles (after clock divider) that a signal needs to stay below

the fine lower threshold limit before the F_LT and IG are

asserted high.

Signal Monitor DC Correction Control (Register 0x10C)

Bit 7—Reserved

Bit 6—DC Correction Freeze

When Bit 6 is set high, the dc correction is no longer updated to

the signal monitor block, which holds the last dc value

calculated.

Bits[5:2]—DC Correction Bandwidth

Bits[5:2] set the averaging time of the signal monitor dc

correction function. This 4-bit word sets the bandwidth of the

correction block, according to the following equation:

−

CLK

Corr

where:

k is the 4-bit value programmed in Bits[5:2] of Register 0x10C

(values between 0 and 13 are valid for k; programming 14 or 15

provides the same result as programming 13).

fCLK is the AD6655 ADC sample rate in hertz (Hz).

Bit 1—DC Correction for Signal Path Enable

Setting this bit high causes the output of the dc measurement

block to be summed with the data in the signal path to remove

the dc offset from the signal path.

Bit 0—DC Correction for Signal Monitor Enable

This bit enables the dc correction function in the signal monitor

block. The dc correction is an averaging function that can be

used by the signal monitor to remove dc offset in the signal.

Removing this dc from the measurement allows a more

accurate power reading.

Signal Monitor DC Value Channel A (Register 0x10D and

These read-only registers hold the latest dc offset value computed

by the signal monitor for Channel A.

AD6655 Datasheet(PDF) 56 Page - Analog Devices

AD6655 Datasheet(HTML) 56 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Datasheet Download

Link URL