AD6655 datasheet(13/84 Pages) AD

13 / 84 page

AD6655

Rev. 0 | Page 13 of 84

SWITCHING SPECIFICATIONS—AD6655BCPZ-80/AD6655BCPZ-105

Table 7.

AD6655BCPZ-80

AD6655BCPZ-105

Parameter

Temp

Min

Typ

Max

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Input Clock Rate

Full

625

MHz

Conversion Rate1

DCS Enabled

Full

105

MSPS

DCS Disabled

Full

105

MSPS

CLK Period—Divide-by-1 Mode (tCLK)

Full

12.5

9.5

CLK Pulse Width High (tCLKH)

Divide-by-1 Mode, DCS Enabled

Full

3.75

6.25

8.75

2.85

4.75

6.65

Divide-by-1 Mode DCS Disabled

Full

5.63

6.25

6.88

4.28

4.75

5.23

Divide-by-2 Mode, DCS Enabled

Full

1.6

Divide-by-3 Through Divide-by-8 Modes, DCS Enabled

Full

0.8

DATA OUTPUT PARAMETERS (DATA, FD)

CMOS Noninterleaved Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD)2

Full

1.6

3.9

6.2

1.6

3.9

6.2

DCO Propagation Delay (tDCO)

Full

4.0

5.4

7.3

4.0

5.4

7.3

Setup Time (tS)

Full

14.0

11.0

Hold Time (tH)

Full

11.0

8.0

CMOS Noninterleaved Mode—DRVDD = 3.3 V

Data Propagation Delay (tPD)2

Full

1.9

4.1

6.4

1.9

4.1

6.4

DCO Propagation Delay (tDCO)

Full

4.4

5.8

7.7

4.4

5.8

7.7

Setup Time (tS)

Full

14.2

11.2

Hold Time (tH)

Full

10.8

7.8

CMOS Interleaved and IQ Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD)2

Full

1.6

3.9

6.2

1.6

3.9

6.2

DCO Propagation Delay (tDCO)

Full

3.4

4.8

6.7

3.4

4.8

6.7

Setup Time (tS)

Full

7.15

5.65

Hold Time (tH)

Full

5.35

3.85

CMOS Interleaved and IQ Mode—DRVDD = 3.3 V

Data Propagation Delay (tPD)2

Full

1.9

4.1

6.4

1.9

4.1

6.4

DCO Propagation Delay (tDCO)

Full

3.8

5.2

7.1

3.8

5.2

7.1

Setup Time (tS)

Full

7.35

5.85

Hold Time (tH)

Full

5.15

3.65

LVDS Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD)2

Full

2.5

4.8

7.0

2.5

4.8

7.0

DCO Propagation Delay (tDCO)

Full

3.7

5.3

7.3

3.7

5.3

7.3

Pipeline Delay (Latency) NCO, FIR, fS/8 Mix Disabled

Full

Cycles

Pipeline Delay (Latency) NCO Enabled, FIR and fS/8 Mix Disabled

(Complex Output Mode)

Full

Cycles

Pipeline Delay (Latency) NCO, FIR, and fS/8 Mix Enabled

Full

109

Cycles

Aperture Delay (tA)

Full

1.0

Aperture Uncertainty (Jitter, tJ)

Full

0.1

ps rms

Wake-Up Time3

Full

350

OUT-OF-RANGE RECOVERY TIME

Full

Cycles

1 Conversion rate is the clock rate after the divider.

2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with a 5 pF load.

3 Wake-up time is dependent on the value of the decoupling capacitors.

AD6655 Datasheet(PDF) 13 Page - Analog Devices

AD6655 Datasheet(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Datasheet Download

Link URL