PCA9535CD datasheet(9/32 Pages) NXP

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PCA9535_PCA9535C_3

Product data sheet

Rev. 03 — 4 October 2007

9 of 32

NXP Semiconductors

PCA9535; PCA9535C

16-bit I2C-bus and SMBus, low power I/O port with interrupt

6.5 Bus transactions

6.5.1 Writing to the port registers

Data is transmitted to the PCA9535/PCA9535C by sending the device address and

setting the least signiﬁcant bit to a logic 0 (see Figure 6 “PCA9535; PCA9535C device

address”). The command byte is sent after the address and determines which register will

receive the data following the command byte.

The eight registers within the PCA9535/PCA9535C are conﬁgured to operate as four

Conﬁguration Ports. After sending data to one register, the next data byte will be sent to

the other register in the pair (see Figure 8 and Figure 9). For example, if the ﬁrst byte is

sent to Output Port 1 (register 3), then the next byte will be stored in Output Port 0

(register 2). There is no limitation on the number of data bytes sent in one write

transmission. In this way, each 8-bit register may be updated independently of the other

registers.

At power-on reset, all registers return to default values.

(1) PCA9535C I/Os are open-drain only. The portion of the PCA9535 schematic marked inside the

dotted line box is not in PCA9535C.

Fig 7.

Simpliﬁed schematic of I/Os

VDD

I/O pin

output port

configuration

data from

shift register

write

configuration

pulse

output port

write pulse

polarity inversion

data from

shift register

write polarity

pulse

input port

read pulse

input port

polarity

inversion

002aac218

data from

shift register

VSS

to INT

(1)

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