8.4 Layout

8.4.1 Layout Guidelines

1. Route the INDP[3:0]P/N and OUTDP[3:0]P/N pairs with controlled 100Ω differential impedance (±10%).

2. Keep away from other high speed signals.

3. Keep intra-pair routing within 5 mils.

4. Keep inter-pair skew within 2 UI according to the DisaplyPort Design Guide

5. Make sure length matching is near the location of mismatch.

6. Separate each pair by at least 3 times the signal trace width.

7. Keep the use of bends in differential traces to a minimum. When bends are used, make sure the number of

left and right bends are as equal as possible and that the angle of the bend is ≥ 135 degrees. This setup

minimizes any length mismatch caused by the bends and therefore minimize the impact bends have on EMI.

8. Route all differential pairs on the same of layer.

9. Keep the number of VIAS to a minimum. TI recommends to keep the VIAS count to 2 or less.

10. The layout can face signal crossing on OUTDP2 and OUTDP3 due to mismatched order between the output

pins of the device and the connector (see Figure 8-7). One option is to do a polarity swap on the input of the

device when GPU is a BGA package to help minimize the number of VIAS being used.

11. Keep traces on layers adjacent to ground plane.

12. Do NOT route differential pairs over any plane split.

13. Remember that adding test points can cause impedance discontinuity, and therefore, negatively impact

signal performance. If test points are used, place the test points in series and symmetrically. Do not place

test points in a manner that causes a stub on the differential pair.

8.4.2 Layout Example

INDP0

INDP1

INDP2

INDP3

OUTDP0

OUTDP1

OUTDP2

OUTDP3

AUX

HPDIN

SNOOPENZ

DPEQ0/A1

I2CEN

A0

DPEQ1

SCL

SDA DPEN

Figure 8-6. Layout Example

TDP142-Q1

SLLSG10A – NOVEMBER 2024 – REVISED FEBRUARY 2025

www.ti.com

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