TDP142 datasheet(8/37 Pages) TI1

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5.8 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

HPDIN

tHPDIN_DEBOUNCE

DPEN and HPDIN debounce time

when transitioning from H to L.

I2C

fSCL

I2C clock frequency

MHz

tBUF

Bus-free time between START and

STOP conditions

Refer to Figure 6-1

0.5

µs

tHDSTA

Hold time after repeated START

condition. After this period, the first

clock pulse is generated

Refer to Figure 6-1

0.26

µs

tLOW

Low period of the I2C clock

Refer to Figure 6-1

0.5

µs

tHIGH

High period of the I2C clock

Refer to Figure 6-1

0.26

µs

tSUSTA

Setup time for a repeated START

condition

Refer to Figure 6-1

0.26

µs

tHDDAT

Data hold time

Refer to Figure 6-1

0.008

µs

tSUDAT

Data setup time

Refer to Figure 6-1

Rise time of both SDA and SCL

signals

Refer to Figure 6-1

120

Fall time of both SDA and SCL signals Refer to Figure 6-1

1.2

120

tSUSTO

Setup time for STOP condition

Refer to Figure 6-1

0.26

µs

Capacitive load for each bus line

150

TDP142-Q1

SLLSG10A – NOVEMBER 2024 – REVISED FEBRUARY 2025

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