5.7 DP Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

AC Characteristics

CPLF-LINRL0

Low-frequency –1dB compression point

at LINR_L0 setting.

At 100MHz, 200mVpp < VID <

1200mVpp, EQ = 0

750

mVppd

CPHF-LINRL0

High-frequency –1dB compression

point at LINR_L0 setting.

At 5GHz, 200mVpp < VID < 1200mVpp,

EQ = 0

675

mVppd

CPLF-LINRL1

Low-frequency –1dB compression point

at LINR_L1 setting.

At 100MHz, 200mVpp < VID <

1200mVpp, EQ = 0

850

mVppd

CPHF-LINRL1

High-frequency –1dB compression

point at LINR_L1 setting.

At 5GHz, 200mVpp < VID < 1200mVpp,

EQ = 0

740

mVppd

CPLF-LINRL2

Low-frequency –1dB compression point

at LINR_L2 setting.

At 100MHz, 200mVpp < VID <

1200mVpp, EQ = 0

975

mVppd

CPHF-LINRL2

High-frequency –1dB compression

point at LINR_L2 setting.

At 5GHz, 200mVpp < VID < 1200mVpp,

EQ = 0

800

mVppd

CPLF-LINRL3

Low-frequency –1dB compression point

at LINR_L3 setting.

At 100MHz, 200mVpp < VID <

1200mVpp, EQ = 0

1050

mVppd

CPHF-LINRL3

High-frequency –1dB compression

point at LINR_L3 setting.

At 5GHz, 200mVpp < VID < 1200mVpp,

EQ = 0

775

mVppd

tTX_DJ

TX output deterministic residual jitter

VID = 0.8Vppd; Optimual EQ setting;

12in prechannel (SDD21 = –8.2dB at

5GHz); 1.6in post channel (SDD21

= –1.8dB at 5GHz); PRBS7; DP at

8.1Gbps

0.06

UI

DisplayPort Receiver

VID(PP)

Peak-to-peak input differential dynamic

voltage range

1400

V

VIC

Input common-mode voltage

0.8

1.75

2

V

VRX_CM-INST

Maximum instantaneous RX DC

common-mode voltage change under

following operating states: OFF to ON,

Disabled to 4DP low power, 4DP active

to Disabled. (1)

Measured single-ended at non-redriver

side of AC-coupling capacitor with

200kΩ load.

–1200

1000

mV

VRX_CM-INST

Maximum instantaneous RX DC

common-mode voltage change under

following operating states: Disabled to

4DP active (D0), D0 to D3, D3 to D0.

Measured single-ended at non-redriver

side of AC-coupling capacitor with 50Ω

load.

–500

1000

mV

dR

Data rate

8.1

Gbps

R(ti)

Input termination resistance

72

90

110

Ω

C(AC)

External required AC-coupling

capacitor

75

265

nF

EQ_DP0

DP0 Receiver equalization at 100MHz

DP0EQ_SEL = 0;

–0.2

dB

EQ_DP15

DP0 Receiver equalization at 100MHz

DP0EQ_SEL = 15;

2.3

dB

EQ_DP0

DP0 Receiver equalization at 4.05GHz

DP0EQ_SEL = 0;

0.6

dB

EQ_DP15

DP0 Receiver equalization at 4.05GHz

DP0EQ_SEL = 15;

14.5

dB

DisplayPort Transmitter

VTX-CM-INST

Maximum instantaneous TX DC

common-mode voltage change for

following operating states: Disabled to

4DP active (D0), D0 to D3, D3 to D0.

Measured at non-redriver side of AC-

coupling capacitor with 50Ω load.

–500

1000

mV

VTX-CM-INST

Maximum instantaneous TX DC

common-mode voltage change under

following operating states: Disabled to

4DP low power, 4DP active to Disabled

Measured at non-redriver side of AC-

coupling capacitor with 200kΩ load.

–1000

1000

mV

VTX(DC-CM)

Common-mode voltage bias in the transmitter (DC)

0.6

1

V

RTX(DIFF)

Differential impedance of the driver

72

90

120

Ω

(1)

Instantaneous common-mode excursions observed by GPU (DPTX) can be minimized by disabling redriver prior to disabling DPTX

termination.

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TDP142-Q1

SLLSG10A – NOVEMBER 2024 – REVISED FEBRUARY 2025

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