2

Interrupt priority levels

8 to 256 priority levels

Wake-up interrupt

controller

Optional

Sleep modes

Integrated WFI and WFE Instructions and Sleep-On

Exit capability

Sleep and deep sleep signals

Optional retention mode with Arm Power Management Kit

Debug

Optional JTAG and serial wire debug ports. Up to

8 breakpoints and 4 watchpoints

Trace

Optional Embedded Trace Macrocell (ETM), Micro Trace

Buffer (MTB), Data Watchpoint and Trace (DWT), and

Instrumentation Trace (ITM)

Optional full data trace with ETM

Dual Core Lock-Step

support (DCLS)

Yes, DCLS configuration

About the Processor

The Cortex-M7 is a high-performance processor with almost double the performance of

the older Cortex-M4. It features a 6-stage superscalar pipeline with branch prediction and

an optional FPU capable of single-precision and optionally double-precision operations. The

instruction and data buses have been enlarged to 64-bit wide over the previous 32-bit buses.

The interfaces that the processor supports include:

64-bit AXI4 interface

32-bit AHB master interface

32-bit AHB slave interface

64-bit instruction TCM interface

2x32-bit data TCM interfaces

The processor has optional:

Up to 64kB instruction cache

Up to 64kB data cache

MPUs which you can configure to protect regions of memory

Double-precision and single-precision FPU

Support for ETM

The processor is highly configurable and is intended for a wide range of high-performance,

deeply embedded applications that require fast interrupt response features.