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Glossary of Terms

AHB

Advanced High-Performance Bus

AHBD

AHB-Lite Debug

AHBP

AHB-Lite Peripheral

AHBS

AHB-Lite slave

ALU

Arithmetic logic units

APB

Advanced Peripheral Bus

ATB

Advanced Trace Bus

AXI

Advanced Extensible Interface

BIC

Bus Interface Unit

BTAC

Branch Target Address Cache

CTI

Cross Trigger Interface Unit

DCLS

Dual Core Lock-step

DMA

Direct Memory Access

DMIPS

Dhrystone Million Instructions per Second

DPU

Data Processing Unit

DSP

Digital Signal Processing

DTCM

Data Tightly Coupled Memory

DWT

Data Watchpoint and Trace

ECC

Error Correction Code

EPPB

External Private Peripheral Bus

ETM

Instruction TraceEmbedded Trace Macrocell

FPU

Floating-point Unit

IEEE

Institute of Electrical and Electronics Engineers

ITCM

Instruction Tightly Coupled Memory

ITM

Instrumentation Trace

JTAG

Joint Test Action Group

LSU

Load Store Unit

MAC

Multiply Accumulate

MBIST

Memory Built-in Self-Test

MHz

Megahertz

MPU

Memory Protection Unit

MTB

Micro Trace Buffer

NMI

Non-maskable Interrupt

NVIC

Nested Vectored Interrupt Controller

Additional Technical documents

1. Cortex-M7 Technical Reference Manual - TRM

2. Cortex-M7 Integration and Implementation Manual – available as part of the Bill of Materials

3. Armv7-M Architecture Reference Manual - Arm

4. CoreSight ETM-M7 Technical Reference Manual - ETM