5

Wake-up Interrupt Controller

The optional Wake-up Interrupt Controller (WIC) provides ultra-low power sleep mode support.

Memory System

The optional memory system includes:

A Bus Interface Unit (BIU) with a configurable AMBA 4 AXI interface that can support

a high-performance L2 memory system

An extended AHB-Lite interface to support low-latency system peripherals

A Tightly Coupled Interface Unit (TCU) with TCM interfaces that can support external

ECC logic and an AHBS interface for system access to TCMs

Instruction and data caches and controllers with optional ECC

A Memory Built-in Self-Test (MBIST) interface. The interface supports MBIST operation

while the processor is running

Memory Protection Unit

The optional MPU has configurable attributes for memory protection. It includes up to 16

memory regions and sub region disable (SRD), enabling efficient use of memory regions.

It also has the ability to enable a background region that implements the default memory

map attributes.

Cortex-M7 Processor and PPB ROM tables

The two ROM tables enable a debugger to identify and connect to CoreSight debug components.

Cross Trigger Interface Unit

The optional Cross Trigger Interface Unit (CTI) enables the debug logic and ETM to interact

with each other and with other CoreSight components.

ETM

The optional Embedded Trace Macrocell provides instruction-only or instruction and data

trace capabilities when configured. See the

Arm CoreSight ETM-M7 Technical Reference

Manual for more information.

Debug and Trace Components

Configurable Breakpoint unit (FPB) for implementing breakpoints

Configurable DWT unit for implementing watchpoints, data tracing, and system profiling

Optional ITM for support of printf() style debugging, using instrumentation trace

Interfaces suitable for:

– Passing on-chip data to a Trace Port Analyzer (TPA), including Single Wire

Output (SWO) mode

– Debugger access to all memory and registers in the system, including access

to memory mapped devices, access to internal core registers when the core

is halted, and access to debug control registers even when reset is asserted