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Arm Cortex-M7 Processor Datasheet

Datasheet

Overview

The

Arm Cortex-M7 processor is the highest-performing processor in the Cortex-M family

that enables the design of sophisticated MCUs and SoCs. The Cortex-M7 offers industry-

leading scalar performance of 5.01 CoreMarks/MHz, while maintaining the excellent

responsiveness and ease-of-use of the Armv7-M architecture. With built-in instruction and

data caches and tightly coupled memories (TCMs) this superscalar processor never has to

slow down even in the most demanding processing applications at the endpoint.

Features

Feature

Description

Architecture

Armv7E-M

ISA support

Thumb/Thumb2

Pipeline

6-stage superscalar and branch prediction

DSP extension

Single-cycle 16/32-bit MAC

Single-cycle dual 16-bit MAC

8/16-bit SIMD arithmetic

Hardware divide

FPU

Optional single and double-precision FPU (choices of none,

single-precision only, and single and double-precision)

IEEE 754 compliant

Interconnect

64-bit AMBA4 AXI, 32-bit AHB peripheral (AHBP) port

32-bit AHB slave (AHBS) port for external master

(such as DMA controller) to access Tightly-Coupled Memories

APB interface for CoreSight debug components

Instruction cache

0 to 64 KB, 2-way associative with optional error correction

code (ECC)

Data cache

0 to 64 KB, 4-way associative with optional ECC

Instruction TCM

0 to 16 MB with optional ECC interface

Data TCM

0 to 16 MB with optional ECC interface

Memory protection

Optional Memory Protection Unit (MPU) with 8 or 16 regions

with sub regions and background regions

Bit manipulation

Integrated Bit-Field Processing Instructions

Interrupts

Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts

Figure 1: Block diagram of the

Cortex-M7 processor