8

Processor Configuration Options

The Cortex-M7 processor has configurable options that you can set during the

implementation and integration stages to match your functional requirements.

Feature

Options

Floating-point

No floating-point

Single-precision floating-point only

Single-precision and double-precision floating-point

Instruction TCM

No instruction TCM

4KB-16MB (powers of 2)

Data TCM

No data TCM

4KB-16MB (powers of 2)

The Data TCM is split equally into two TCMs, D0TCM, and

D1TCM

Instruction cache

No instruction cache controller

Instruction cache controller is included

Data cache

Area optimized AXIM interface, no data cache

Performance optimized AXIM interface, data cache included

Instruction cache size

4KB, 8KB, 16KB, 32KB, 64KB

Data cache size

4KB, 8KB, 16KB, 32KB, 64KB

AHB peripheral size

64KB, 128KB, 256KB, 512MB

ECC support on caches

No ECC on instruction cache or data cache

ECC on all implemented caches

Protected memory

regions

0 region, 8 regions, 16 regions

Interrupts

1-240 interrupts

Number bits of interrupt

priority

Between 3 and 8 bits of interrupt priority, 8 and 256 levels

of priority

Debug watchpoints

and breakpoints

Reduced set. 2 data watchpoints comparators and 4 breakpoint

comparators

Full set. 4 data watchpoints comparators and 8 breakpoint

comparators

ITM and DWT trace

functionality

No ITM or DWT trace

Complete ITM and DWT trace

ETM

No ETM support

ETM instruction trace only

ETM instruction and data trace

Dual-redundant

processor

No dual-redundant processor

Dual-redundant processor included

Reset all registers

Only required registers that must be initialized are reset

in the RTL

All registers are reset in the RTL excluding those in the ETM,

if included

All registers are reset in the RTL including those in the ETM,

if included

Cross Trigger Interface

(CTI)

No CTI

CTI included

WIC

No WIC

WIC included