6

Interfaces

The processor contains the following external interfaces:

AHBP interface

AHBS interface

AHBD interface

External Private Peripheral Bus

ATB interfaces

TCM interface

Cross Trigger interface

MBIST interface

AXIM interface

AHBP Interface

The AHBP interface provides access suitable for low latency system peripherals. It provides support

for unaligned memory accesses, write buffer for buffering of write data, and exclusive access

transfers for multiprocessor systems.

AHBS Interface

The AHBS interface enables system access to TCMs.

AHBD Interface

The AHB-Lite Debug (AHBD) interface provides debug access to the Cortex-M7 processor and

the complete memory map.

External Private Peripheral Bus

The APB External PPB (EPPB) enables access to CoreSight-compatible debug and trace

components, in the system connected to the processor.

ATB Interfaces

The ATB interface output traces information used for debugging. The ATB interface is compatible

with the CoreSight architecture. See the

Arm CoreSightTM Architecture Specification (v2.0) for

more information.

TCM Interface

The processor can have up to two TCM memory instances, Instruction TCM (ITCM) and Data

TCM (DTCM), each with a double word data width. Access to ITCM is through the ITCM 64-bit

wide interface. Access to DTCM is through the 32-bit D0TCM interface and the 32-bit wide

D1TCM interface. The DTCM accesses are split so that lower words always access D0TCM and

upper words always access D1TCM. The size of both TCM instances is configurable, 4KB-16MB in

powers of 2.