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Block Diagram

Cortex-M7 processor components

Cortex-M7 Processor Components

Data Processing Unit

The Data Processing Unit (DPU) provides:

Parallelized integer register file with six read ports and four write ports for large-scale

dual-issue

Extensive forwarding logic to minimise interlocks

Two Arithmetic Logic Units (ALUs), with one ALU capable of executing SIMD operations

Single MAC pipeline capable of 32x32-bit + 64-bit → 64-bit with two cycle result

latency and one MAC per cycle throughput

Single divider unit with support for operand-dependent early termination

Prefetch Unit

The Prefetch Unit (PFU) provides:

64-bit instruction fetch bandwidth

Four 64-bit prefetch queue to decouple instruction prefetch from

DPU pipeline operation

A Branch Target Address Cache (BTAC) for single-cycle turn-around of branch predictor

state and target address

Figure 2: Cortex-M7

processor components