4

A static branch predictor when no BTAC is specified

Forwarding of flags for early resolution of direct branches in the decoder and first

execution stages of the processor pipeline

Load Store Unit

The Load Store Unit (LSU) provides:

Dual 32-bit load channels to TCM, data cache, and AXI master (AXIM) interface

for 64-bit load bandwidth and dual 32-bit load capability

Single 32-bit load channel to the AHB interface. Single 64-bit store channel

Store buffering to increase store throughput and minimize RAM contention with data

and instruction reads

Separate store buffering for TCM, AHBP and AXIM for quality of service (QoS) and

interface-specific optimizations

Floating-point Unit

The optional FPU provides:

Lazy floating-point context save. Automated stacking of floating-point state is delayed

until the ISR attempts to execute a floating-point instruction. This reduces the latency

to enter the ISR and removes floating-point context save for ISRs that do not use

floating-point

Instructions for single-precision (C programming language float type)

data-processing operations

Optional instructions for double-precision (C double type) data-processing operations

Combined multiply and accumulate instructions for increased precision (Fused MAC)

Hardware support for conversion, addition, subtraction, multiplication with optional

accumulate, division, and square root

Hardware support for denormals and all IEEE Standard 754-2008 rounding modes

32 x 32-bit single-precision registers or 16 x 64-bit double-precision registers

Nested Vectored Interrupt Controller

The NVIC is closely integrated with the core to achieve low-latency interrupt processing.

Features include:

External interrupts, configurable from 1 to 240. This is configured at implementation

Configurable levels of interrupt priority from 8 to 256. Configured at implementation

Dynamic reprioritization of interrupts

Priority grouping. This enables selection of pre-empting interrupt levels and

non-pre-empting interrupt levels

Support for tail-chaining and late arrival of interrupts. This enables back-to-back interrupt

processing without the overhead of state saving and restoration between interrupts