AX88780 datasheet(54/55 Pages) ASIX

54 / 55 page

AX88780

ASIX ELECTRONICS CORPORATION

Revision History

Revision

Date

Comment

V1.0

2005/10/4

First edition

V1.1

2006/7/28

1. Some typo errors corrected between Pin diagram and tables.

2. Host read/write timing revised in Section 5.

3. Some bits of registers are updated.

4. Add some connections between MCU and AX88780 in Appendix.

5. Add wake up LAN description in Appendix.

V1.2

2007/3/28

1. Correct some information in Section 3.9 for 16-bit mode operation.

2. Modify the data access timing information in Section 6.2.5, 6.2.6, 6.2.10 and

Appendix A3.

3. Change the default value of PHYIDR1 register for version 3.

4. Add some information in Section 3.11.

5. Modify some descriptions in Section 1.1, 4.6, 4.17, 4.18, 4.19, 4.23,

4.35~37, 4.41.

6. Rearrange the content of Appendix into Appendix A1~A4.

7. Change the number format from 16h’XXXX to 0xXXXX for example.

V1.3

2007/5/4

Swap the XTLN and XTLP pin definitions in Section 2.7.

Correct some typo errors of pin type in Table 4 and Table 6.

V1.4

2007/5/18

Modify max operation frequency of HCLK from 125MHz to 100MHz.

Modify some thermal information in Section 6.1.9.

AX88780 Datasheet(PDF) 54 Page - ASIX Electronics Corporation