AX88780

6

ASIX ELECTRONICS CORPORATION

List of Figures

Figure 1: AX88780 block diagram ....................................................................................................................................... 7

Figure 2: AX88780 pin connection diagram......................................................................................................................... 8

Figure 3: 32-bit mode address mapping................................................................................................................................ 13

Figure 4: data swap block ..................................................................................................................................................... 14

Figure 5: 16-bit mode address mapping................................................................................................................................ 15

Figure 6: Transmit waveform specification .......................................................................................................................... 39

List of Tables

Table 1 : Host Interface signals group ......................................................................................................................................9

Table 2: EEPROM Interface signals group.............................................................................................................................10

Table 3: Regulator signals group ............................................................................................................................................11

Table 4: 10/100M Twisted-pair signals group.........................................................................................................................11

Table 5: MII Interface signals group.......................................................................................................................................11

Table 6: Miscellaneous signals group .....................................................................................................................................12

Table 7: Power/Ground pins group .........................................................................................................................................12

Table 8: MAC Register Mapping............................................................................................................................................17

Table 9 : PHY Register Mapping ............................................................................................................................................34