March 26, 2021

3.2

ES9016K2M Datasheet

27

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-

8800 • www.esstech.com

XI / MCLK Timing

t

MCH

t

MCL

t

MCY

MCLK

t

MCH

t

MCL

t

MCY

MCLK

Parameter

Symbol

Min

Max

Unit

MCLK pulse width high

TMCH

4.5

ns

MCLK pulse width low

TMCL

4.5

ns

MCLK cycle time

TMCY

10

ns

MCLK duty cycle

45:55

55:45

Audio Interface Timing

L

t

DCH

t

DCL

t

DCY

DATA_CLK

t

DH

t

DS

DATA[8:1]

Valid

Invalid

Valid

t

DCH

t

DCL

t

DCY

DATA_CLK

t

DH

t

DS

DATA[8:1]

Valid

Invalid

Valid

DATA_CLK

DATA[2:1]

Parameter

Symbol

Min

Max

Unit

DATA_CLK pulse width high

tDCH

4.5

ns

DATA_CLK pulse width low

tDCL

4.5

ns

DATA_CLK cycle time

tDCY

10

ns

DATA_CLK duty cycle

45:55

55:45

DATA set-up time to DATA_CLK rising edge

tDS

4.1

ns

DATA hold time to DATA_CLK rising edge

tDH

2

ns

Notes:

•

Audio data on DATA[2:1] are sampled at the rising edges of DATA_CLK and must satisfy the setup and hold time

requirements relative to the rising edge of DATA_CLK

•

For DSD Phase mode, the normal data (D0, D1, D2.. on p.10) must satisfy the setup and hold time requirements relative

to the rising edge of DATA_CLK. The complimentary data (D0, D1, etc.) will be ignored.