ADS5232 datasheet(21/30 Pages) TI2

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External Reference

SNR + 20LOG10

2p f

IN t JA

(1)

PLL CONTROL

OUTPUT INFORMATION

CLOCK INPUT

ADS5232

SBAS294A – JUNE 2004 – REVISED MARCH 2006

dominant in maintaining a good signal-to-noise ratio

(SNR).

This

condition

particularly

critical

The ADS5232 also supports the use of external

IF-sampling applications; for example, where the

reference voltages. External reference voltage mode

sampling frequency is lower than the input frequency

involves applying an external top reference at REFT

(under-sampling). The following equation can be used

(pin 53) and a bottom reference at REFB (pin 54).

to calculate the achievable SNR for a given input

Setting the ADS5232 for external reference mode

frequency and clock jitter (tJA in psRMS):

also requires taking the INT/EXT pin low. In this

mode, the internal reference buffer is tri-stated. Since

the switching current for the two ADC channels

comes from the externally-forced references, it is

The ADS5232 will enter into a power-down mode if

possible for the device performance to be slightly

the sampling clock rate drops below a limit of

lower than when the internal references are used. It

approximately

2MSPS.

the

sampling

rate

should be noted that in external reference mode, VCM

increased above this threshold, the ADS5232 will

and ISET continue to be generated from the internal

automatically resume normal operation.

bandgap voltage, as they are in the internal reference

mode. Therefore, it is important to ensure that the

common-mode

voltage

the

externally-forced

reference voltages matches to within 50mV of VCM

The ADS5232 has an internal PLL that is enabled by

(+1.5VDC).

default. The PLL enables a wide range of clock duty

cycles. Good performance is obtained for duty cycles

The external reference circuit must be designed to

up to 40%–60%, though the ensured electrical

drive the internal reference impedance seen between

specifications presume that the duty cycle is between

the REFT and REFB pins. To establish the drive

45%–55%. The PLL automatically limits the minimum

requirements, consider that the external reference

frequency of operation to 20MSPS. For operation

circuit needs to supply an average switching current

below 20MSPS, the

PLL

can

disabled

of at least 1mA. This dynamic switching current

programming the internal registers through the serial

depends on the actual device sampling rate and the

interface. With the PLL disabled, the clock speed can

signal level. The external reference voltages can vary

go down to 2MSPS. With the PLL disabled, the clock

as long as the value of the external top reference

duty cycle needs to be constrained closer to 50%.

stays within the range of +1.875V to +2.0V, and the

external bottom reference stays within +1.0V to

+1.125V. Consequently, the full-scale input range can

be set between 1.5VPP and 2VPP (FSR = 2x [REFT –

The ADS5232 provides two channels with 12 data

REFB] ).

outputs (D11 to D0, with D11 being the MSB and D0

the LSB), data-valid outputs (DVA, DVB, pin 26 and

pin 22, respectively), and individual out-of-range

indicator output pins (OVRA/OVRB, pin 39 and pin 9,

The ADS5232 requires a single-ended clock source.

respectively).

The clock input, CLK, represents a CMOS-compatible

logic input with an input impedance of about 5pF. For

The output circuitry of the ADS5232 has been

high input frequency sampling, it is recommended to

designed

minimize

the

noise

produced

use a clock source with very low jitter. A low-jitter

transients of the data switching, and in particular its

clock is essential in order to preserve the excellent ac

coupling to the ADC analog circuitry.

performance of the ADS5232. The converter itself is

specified for a low 1.0ps (rms) jitter. Generally, as the

input frequency increases, clock jitter becomes more

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