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RECOMMENDED POWER-UP SEQUENCING

t

1

t

3

t

5

t

6

t

4

t

7

t

8

t

2

AVDD (3V to 3.6V)

VDRV (3V to 3.6V)

Device Ready

For ADC Operation

Device Ready

For ADC Operation

Device Ready

For Serial Register Write

Start of Clock

AVDD

VDRV

SEL

SEN

CLK

NOTE: 10

µs < t

1 < 50ms; 10µs < t2 < 50ms; −10ms < t3 < 10ms; t4 > 10ms; t5 > 100ns; t6 > 100ns; t7 > 10ms; and t8 > 100µs.

STPD

Device Fully

Powers Down

Device Fully

Powers Up

500

µs

1

µs

NOTE: The shown power−up time is based on 1

µF bypass capacitors on the reference pins.

See the Theory of Operation section for details.

ADS5232

SBAS294A – JUNE 2004 – REVISED MARCH 2006

Shown for the case where the serial interface is used.

POWER-DOWN TIMING

11

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