OPA690 datasheet(20/33 Pages) TI2

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OPA699

SBOS261D

www.ti.com

When the limiter voltages are more than 2.1V from the

supplies (VL ≥ –VS + 2.1V or VH ≤ +VS – 2.1V), you can use

simple resistor dividers to set VH and VL (see Figure 1). Make

sure to include the limiter input bias currents (Figure 8) in the

calculations (that is, IVL = 50µA into pin 5, and IVH = +50µA

out of pin 8). For good limiter voltage accuracy, run a

minimum 1mA quiescent bias current through these resis-

tors. When the limiter voltages need to be within 2.1V of the

supplies (VL ≤ –VS + 2.1V or VH ≥ +VS – 2.1V), consider using

low impedance buffers to set VH and VL to minimize errors

due to bias current uncertainty. This condition will typically be

the case for single-supply operation (VS = +5V). Figure 2

runs 2.5mA through the resistive divider that sets VH and VL.

This limits errors due to IVH and IVL < ±1% of the target limit

voltages. The limiters’ DC accuracy depends on attention to

detail. The two dominant error sources can be improved as

follows:

• Power supplies, when used to drive resistive dividers that

set VH and VL, can contribute large errors (for example,

±5%). Using a more accurate source, and bypassing pins

5 and 8 with good capacitors, will improve limiter PSRR.

• The resistor tolerances in the resistive divider can also

dominate. Use 1% resistors.

Other error sources also contribute, but should have little

impact on the limiters’ DC accuracy:

• Reduce offsets caused by the Limiter Input Bias Currents.

Select the resistors in the resistive divider(s) as described

above.

• Consider the signal path DC errors as contributing to

uncertainty in the useable output swing.

• The limiter offset voltage only slightly degrades limiter

accuracy. Figure 13 shows how the limiters affect distor-

tion performance. Virtually no degradation in linearity is

observed for output voltage swinging right up to the limiter

voltages. In this plot a fixed

±1V output swing is driven

while the limiter voltages are reduced symmetrically. Until

the limiters are reduced to

±1.1V, little distortion degrada-

tion is observed.

OUTPUT DRIVE

The OPA699 has been optimized to drive 500

Ω loads, such

as ADCs. It still performs very well driving 100

Ω loads; the

specifications are shown for the 500

Ω load. This makes the

OPA699 an ideal choice for a wide range of high-frequency

applications.

Many high-speed applications, such as driving ADCs, require

op amps with low output impedance. As shown in the typical

performance curve

Output Impedance vs Frequency, the

OPA699 maintains very low closed-loop output impedance

over frequency. Closed-loop output impedance increases

with frequency, since loop gain decreases with frequency.

THERMAL CONSIDERATIONS

The OPA699 will not require heat sinking under most oper-

ating conditions. Maximum desired junction temperature will

set a maximum allowed internal power dissipation as de-

scribed below. In no case should the maximum junction

temperature be allowed to exceed 150

°C.

The total internal power dissipation (PD) is the sum of

quiescent power (PDQ) and the additional power dissipated in

the output stage (PDL) while delivering load power. PDQ is

simply the specified no-load supply current times the total

supply voltage across the part. PDL depends on the required

output signals and loads. For a grounded resistive load, and

equal bipolar supplies, it is at maximum when the output is

at 1/2 either supply voltage. In this condition, PDL = VS2/(4RL)

where RL includes the feedback network loading. Note that it

is the power in the output stage, and not in the load, that

determines internal power dissipation.

The operating junction temperature is: TJ = TA + PD x θJA,

where TA is the ambient temperature. For example, the

maximum TJ for a OPA699ID with G = +6, RF = 750Ω,

RL = 500Ω, and ±VS = ±5V at the maximum TA = +85°C is

calculated as:

PmW

C W

=×

(

) =

( )

(

)

=° +

15 5

155

500

900

19 4

155

19 4

174 4

125

107

ΩΩ

This would be the maximum TJ from VO = ±2.5VDC. Most

applications will be at a lower output stage power and have

a lower TJ.

CAPACITIVE LOADS

Capacitive loads, such as the input to ADCs, will decrease

the amplifier phase margin, which may cause high-frequency

peaking or oscillations. Capacitive loads

≥ 2pF should be

isolated by connecting a small resistor in series with the

output, as shown in Figure 14. Increasing the gain from +2

will improve the capacitive drive capabilities due to increased

phase margin.

± Limit Voltage (V)

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7 1.8

1.9

2.0

−40

−50

−60

−70

−80

−90

3rd-Harmonic

2nd-Harmonic

O = 0VDC ± 1VP

f = 5MHz

L = 500Ω

FIGURE 13. Harmonic Distortion Near Limit Voltages.

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