PCI2040 datasheet(24/79 Pages) TI2

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3−5

•

HPI CSR memory base address register (see Section 4.11) is programmed to provide a pointer to the HPI

control and status registers (see Section 5). HPI CSR I/O base address register (see Section 4.32) can also

be programmed to give I/O access.

•

Control space base address register (see Section 4.12) is programmed and 32K bytes of memory are

allocated.

•

The PCI command register (see Section 4.3) is programmed to allow PCI2040 to respond to memory and

I/O cycles.

•

Software must clear the HPI reset register (see Section 5.4) to remove the reset assertion to the DSPs.

•

When PCI2040 decodes a PCI address within the 32-Kbyte memory control space window, it claims the

cycle and decodes the chip select, HCNTL1 and HCNTL0, to pass to the HPI interface.

•

The host initializes the BOB or HWOB bit in the HPI control register (see Section 6.2 or Section 6.3.5,

respectively) to choose the correct byte alignment. This results in an HPI cycle to the DSP’s HPI control

•

The host then initializes the HPI address register with the correct HPI memory address. By loading the HPI

address register, an internal DSP HPI memory access is initiated and the data is latched in the HPI data

•

If this is a read:

−

The host performs a read of the HPI data register. During the read, the contents of the first half-word data

latch appear on the HADn pins when the HWIL signal is low and contents of the second data latch when

the HWIL signal is high.

−

If auto-increment is selected, then it occurs between the transfer of the first and second bytes. This

allows back-to-back HPI data register accesses without an intervening HPI address register access.

•

If this is a write:

−

The first data latch of HPI data register is written from the data coming from the host while HWIL is low

and the second data latch when HWIL is high. If communicating with C6x, then the correct combination

of byte enables must also be used.

−

If auto-increment is selected, then it occurs between the transfer of the first and second bytes.

3.5.6

HPI Interface Specific Notes

The PCI2040 supports the HPI features from C54x and C6x interfaces given in Table 3−2. See Section 6, DSP HPI

Overview, and the HPI functional specification and timing requirements for more details.

Table 3−2. HPI Interface Features

C54x

C6x

Shared access mode (SAM) and host only mode (HOM)

Only one mode of operation: host only mode (HOM)

Auto-increment

Endian byte swap (BOB)

Endian byte swap (HWOB)

DSP-to-host interrupt

Wait states using HRDY5xn

Wait states using HRDY6xn

Two data strobes: HDS, HR/W

HPI memory access during reset

Byte enables

No software handshaking using HRDY and FETCH

Valid byte enables

All byte enables valid

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